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Nellyw888
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VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb
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Reinforcement Learning
Transformers
Safetensors
Nellyw888/RTL-Coder_7b_reasoning_tb
Nellyw888/RTL-Coder_7b_reasoning_tb_simple
qwen2
text-generation
verilog
reasoning
rtl
text-generation-inference
arxiv:
2505.11849
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58652c2
VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb
6.19 GB
1 contributor
History:
136 commits
Nellyw888
Training in progress, step 430
58652c2
verified
7 months ago
.gitattributes
1.57 kB
Training in progress, step 5
7 months ago
added_tokens.json
605 Bytes
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7 months ago
chat_template.jinja
2.51 kB
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7 months ago
config.json
691 Bytes
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7 months ago
merges.txt
1.67 MB
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7 months ago
model-00001-of-00002.safetensors
4.96 GB
xet
Training in progress, step 430
7 months ago
model-00002-of-00002.safetensors
1.21 GB
xet
Training in progress, step 430
7 months ago
model.safetensors.index.json
35.6 kB
Training in progress, step 5
7 months ago
special_tokens_map.json
613 Bytes
Training in progress, step 5
7 months ago
tokenizer.json
11.4 MB
xet
Training in progress, step 5
7 months ago
tokenizer_config.json
4.71 kB
Training in progress, step 5
7 months ago
training_args.bin
8.7 kB
xet
Training in progress, step 430
7 months ago
vocab.json
2.78 MB
Training in progress, step 5
7 months ago
