PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus,

                     qemu_irq *p_rtc_irq,

                     AlphaCPU *cpus[4], pci_map_irq_fn sys_map_irq)

{

    const uint64_t MB = 1024 * 1024;

    const uint64_t GB = 1024 * MB;

    MemoryRegion *addr_space = get_system_memory();

    MemoryRegion *addr_space_io = get_system_io();

    DeviceState *dev;

    TyphoonState *s;

    PCIHostState *phb;

    PCIBus *b;

    int i;

    dev = qdev_create(NULL, TYPE_TYPHOON_PCI_HOST_BRIDGE);

    qdev_init_nofail(dev);

    s = TYPHOON_PCI_HOST_BRIDGE(dev);

    phb = PCI_HOST_BRIDGE(dev);

    /* Remember the CPUs so that we can deliver interrupts to them.  */

    for (i = 0; i < 4; i++) {

        AlphaCPU *cpu = cpus[i];

        s->cchip.cpu[i] = cpu;

        if (cpu != NULL) {

            CPUAlphaState *env = &cpu->env;

            env->alarm_timer = qemu_new_timer_ns(rtc_clock,

                                                 typhoon_alarm_timer,

                                                 (void *)((uintptr_t)s + i));

        }

    }

    *p_rtc_irq = *qemu_allocate_irqs(typhoon_set_timer_irq, s, 1);

    /* Main memory region, 0x00.0000.0000.  Real hardware supports 32GB,

       but the address space hole reserved at this point is 8TB.  */

    memory_region_init_ram(&s->ram_region, "ram", ram_size);

    vmstate_register_ram_global(&s->ram_region);

    memory_region_add_subregion(addr_space, 0, &s->ram_region);

    /* TIGbus, 0x801.0000.0000, 1GB.  */

    /* ??? The TIGbus is used for delivering interrupts, and access to

       the flash ROM.  I'm not sure that we need to implement it at all.  */

    /* Pchip0 CSRs, 0x801.8000.0000, 256MB.  */

    memory_region_init_io(&s->pchip.region, &pchip_ops, s, "pchip0", 256*MB);

    memory_region_add_subregion(addr_space, 0x80180000000ULL,

                                &s->pchip.region);

    /* Cchip CSRs, 0x801.A000.0000, 256MB.  */

    memory_region_init_io(&s->cchip.region, &cchip_ops, s, "cchip0", 256*MB);

    memory_region_add_subregion(addr_space, 0x801a0000000ULL,

                                &s->cchip.region);

    /* Dchip CSRs, 0x801.B000.0000, 256MB.  */

    memory_region_init_io(&s->dchip_region, &dchip_ops, s, "dchip0", 256*MB);

    memory_region_add_subregion(addr_space, 0x801b0000000ULL,

                                &s->dchip_region);

    /* Pchip0 PCI memory, 0x800.0000.0000, 4GB.  */

    memory_region_init(&s->pchip.reg_mem, "pci0-mem", 4*GB);

    memory_region_add_subregion(addr_space, 0x80000000000ULL,

                                &s->pchip.reg_mem);

    /* Pchip0 PCI I/O, 0x801.FC00.0000, 32MB.  */

    /* ??? Ideally we drop the "system" i/o space on the floor and give the

       PCI subsystem the full address space reserved by the chipset.

       We can't do that until the MEM and IO paths in memory.c are unified.  */

    memory_region_init_io(&s->pchip.reg_io, &alpha_pci_bw_io_ops, NULL,

                          "pci0-io", 32*MB);

    memory_region_add_subregion(addr_space, 0x801fc000000ULL,

                                &s->pchip.reg_io);

    b = pci_register_bus(dev, "pci",

                         typhoon_set_irq, sys_map_irq, s,

                         &s->pchip.reg_mem, addr_space_io, 0, 64);

    phb->bus = b;

    /* Pchip0 PCI special/interrupt acknowledge, 0x801.F800.0000, 64MB.  */

    memory_region_init_io(&s->pchip.reg_iack, &alpha_pci_iack_ops, b,

                          "pci0-iack", 64*MB);

    memory_region_add_subregion(addr_space, 0x801f8000000ULL,

                                &s->pchip.reg_iack);

    /* Pchip0 PCI configuration, 0x801.FE00.0000, 16MB.  */

    memory_region_init_io(&s->pchip.reg_conf, &alpha_pci_conf1_ops, b,

                          "pci0-conf", 16*MB);

    memory_region_add_subregion(addr_space, 0x801fe000000ULL,

                                &s->pchip.reg_conf);

    /* For the record, these are the mappings for the second PCI bus.

       We can get away with not implementing them because we indicate

       via the Cchip.CSC<PIP> bit that Pchip1 is not present.  */

    /* Pchip1 PCI memory, 0x802.0000.0000, 4GB.  */

    /* Pchip1 CSRs, 0x802.8000.0000, 256MB.  */

    /* Pchip1 PCI special/interrupt acknowledge, 0x802.F800.0000, 64MB.  */

    /* Pchip1 PCI I/O, 0x802.FC00.0000, 32MB.  */

    /* Pchip1 PCI configuration, 0x802.FE00.0000, 16MB.  */

    /* Init the ISA bus.  */

    /* ??? Technically there should be a cy82c693ub pci-isa bridge.  */

    {

        qemu_irq isa_pci_irq, *isa_irqs;

        *isa_bus = isa_bus_new(NULL, addr_space_io);

        isa_pci_irq = *qemu_allocate_irqs(typhoon_set_isa_irq, s, 1);

        isa_irqs = i8259_init(*isa_bus, isa_pci_irq);

        isa_bus_irqs(*isa_bus, isa_irqs);

    }

    return b;

}


static int decode_update_thread_context(AVCodecContext *dst, const AVCodecContext *src){

    H264Context *h= dst->priv_data, *h1= src->priv_data;

    MpegEncContext * const s = &h->s, * const s1 = &h1->s;

    int inited = s->context_initialized, err;

    int i;

    if(dst == src || !s1->context_initialized) return 0;

    err = ff_mpeg_update_thread_context(dst, src);

    if(err) return err;

    //FIXME handle width/height changing

    if(!inited){

        for(i = 0; i < MAX_SPS_COUNT; i++)

            av_freep(h->sps_buffers + i);

        for(i = 0; i < MAX_PPS_COUNT; i++)

            av_freep(h->pps_buffers + i);

        memcpy(&h->s + 1, &h1->s + 1, sizeof(H264Context) - sizeof(MpegEncContext)); //copy all fields after MpegEnc

        memset(h->sps_buffers, 0, sizeof(h->sps_buffers));

        memset(h->pps_buffers, 0, sizeof(h->pps_buffers));

        ff_h264_alloc_tables(h);

        context_init(h);

        for(i=0; i<2; i++){

            h->rbsp_buffer[i] = NULL;

            h->rbsp_buffer_size[i] = 0;

        }

        h->thread_context[0] = h;

        // frame_start may not be called for the next thread (if it's decoding a bottom field)

        // so this has to be allocated here

        h->s.obmc_scratchpad = av_malloc(16*2*s->linesize + 8*2*s->uvlinesize);

        s->dsp.clear_blocks(h->mb);

    }

    //extradata/NAL handling

    h->is_avc          = h1->is_avc;

    //SPS/PPS

    copy_parameter_set((void**)h->sps_buffers, (void**)h1->sps_buffers, MAX_SPS_COUNT, sizeof(SPS));

    h->sps             = h1->sps;

    copy_parameter_set((void**)h->pps_buffers, (void**)h1->pps_buffers, MAX_PPS_COUNT, sizeof(PPS));

    h->pps             = h1->pps;

    //Dequantization matrices

    //FIXME these are big - can they be only copied when PPS changes?

    copy_fields(h, h1, dequant4_buffer, dequant4_coeff);

    for(i=0; i<6; i++)

        h->dequant4_coeff[i] = h->dequant4_buffer[0] + (h1->dequant4_coeff[i] - h1->dequant4_buffer[0]);

    for(i=0; i<2; i++)

        h->dequant8_coeff[i] = h->dequant8_buffer[0] + (h1->dequant8_coeff[i] - h1->dequant8_buffer[0]);

    h->dequant_coeff_pps = h1->dequant_coeff_pps;

    //POC timing

    copy_fields(h, h1, poc_lsb, redundant_pic_count);

    //reference lists

    copy_fields(h, h1, ref_count, intra_gb);

    copy_fields(h, h1, short_ref, cabac_init_idc);

    copy_picture_range(h->short_ref,   h1->short_ref,   32, s, s1);

    copy_picture_range(h->long_ref,    h1->long_ref,    32,  s, s1);

    copy_picture_range(h->delayed_pic, h1->delayed_pic, MAX_DELAYED_PIC_COUNT+2, s, s1);

    h->last_slice_type = h1->last_slice_type;

    if(!s->current_picture_ptr) return 0;

    if(!s->dropable) {

        ff_h264_execute_ref_pic_marking(h, h->mmco, h->mmco_index);

        h->prev_poc_msb     = h->poc_msb;

        h->prev_poc_lsb     = h->poc_lsb;

    }

    h->prev_frame_num_offset= h->frame_num_offset;

    h->prev_frame_num       = h->frame_num;

    h->outputed_poc         = h->next_outputed_poc;

    return 0;

}


static int device_open(AVFormatContext *ctx)

{

    struct v4l2_capability cap;

    int fd;

#if CONFIG_LIBV4L2

    int fd_libv4l;

#endif

    int res, err;

    int flags = O_RDWR;

    if (ctx->flags & AVFMT_FLAG_NONBLOCK) {

        flags |= O_NONBLOCK;

    }

    fd = v4l2_open(ctx->filename, flags, 0);

    if (fd < 0) {

        err = errno;

        av_log(ctx, AV_LOG_ERROR, "Cannot open video device %s : %s\n",

               ctx->filename, strerror(err));

        return AVERROR(err);

    }

#if CONFIG_LIBV4L2

    fd_libv4l = v4l2_fd_open(fd, 0);

    if (fd < 0) {

        err = AVERROR(errno);

        av_log(ctx, AV_LOG_ERROR, "Cannot open video device with libv4l neither %s : %s\n",

               ctx->filename, strerror(errno));

        return err;

    }

    fd = fd_libv4l;

#endif

    res = v4l2_ioctl(fd, VIDIOC_QUERYCAP, &cap);

    if (res < 0) {

        err = errno;

        av_log(ctx, AV_LOG_ERROR, "ioctl(VIDIOC_QUERYCAP): %s\n",

               strerror(err));

        goto fail;

    }

    av_log(ctx, AV_LOG_VERBOSE, "[%d]Capabilities: %x\n",

           fd, cap.capabilities);

    if (!(cap.capabilities & V4L2_CAP_VIDEO_CAPTURE)) {

        av_log(ctx, AV_LOG_ERROR, "Not a video capture device.\n");

        err = ENODEV;

        goto fail;

    }

    if (!(cap.capabilities & V4L2_CAP_STREAMING)) {

        av_log(ctx, AV_LOG_ERROR,

               "The device does not support the streaming I/O method.\n");

        err = ENOSYS;

        goto fail;

    }

    return fd;

fail:

    v4l2_close(fd);

    return AVERROR(err);

}


int pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t type, uint8_t port)

{

    /* PCIe cap v2 init */

    int pos;

    uint8_t *exp_cap;

    assert(pci_is_express(dev));

    pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset, PCI_EXP_VER2_SIZEOF);

    if (pos < 0) {

        return pos;

    }

    dev->exp.exp_cap = pos;

    exp_cap = dev->config + pos;

    /* Filling values common with v1 */

    pcie_cap_v1_fill(exp_cap, port, type, PCI_EXP_FLAGS_VER2);

    /* Filling v2 specific values */

    pci_set_long(exp_cap + PCI_EXP_DEVCAP2,

                 PCI_EXP_DEVCAP2_EFF | PCI_EXP_DEVCAP2_EETLPP);

    pci_set_word(dev->wmask + pos + PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_EETLPPB);

    return pos;

}


void ff_svq3_add_idct_c(uint8_t *dst, DCTELEM *block, int stride, int qp,

                            int dc)

{

    const int qmul = svq3_dequant_coeff[qp];

    int i;

    uint8_t *cm = ff_cropTbl + MAX_NEG_CROP;

    if (dc) {

        dc = 13*13*((dc == 1) ? 1538*block[0] : ((qmul*(block[0] >> 3)) / 2));

        block[0] = 0;

    }

    for (i = 0; i < 4; i++) {

        const int z0 = 13*(block[0 + 4*i] +    block[2 + 4*i]);

        const int z1 = 13*(block[0 + 4*i] -    block[2 + 4*i]);

        const int z2 =  7* block[1 + 4*i] - 17*block[3 + 4*i];

        const int z3 = 17* block[1 + 4*i] +  7*block[3 + 4*i];

        block[0 + 4*i] = z0 + z3;

        block[1 + 4*i] = z1 + z2;

        block[2 + 4*i] = z1 - z2;

        block[3 + 4*i] = z0 - z3;

    }

    for (i = 0; i < 4; i++) {

        const int z0 = 13*(block[i + 4*0] +    block[i + 4*2]);

        const int z1 = 13*(block[i + 4*0] -    block[i + 4*2]);

        const int z2 =  7* block[i + 4*1] - 17*block[i + 4*3];

        const int z3 = 17* block[i + 4*1] +  7*block[i + 4*3];

        const int rr = (dc + 0x80000);

        dst[i + stride*0] = cm[ dst[i + stride*0] + (((z0 + z3)*qmul + rr) >> 20) ];

        dst[i + stride*1] = cm[ dst[i + stride*1] + (((z1 + z2)*qmul + rr) >> 20) ];

        dst[i + stride*2] = cm[ dst[i + stride*2] + (((z1 - z2)*qmul + rr) >> 20) ];

        dst[i + stride*3] = cm[ dst[i + stride*3] + (((z0 - z3)*qmul + rr) >> 20) ];

    }

}


void process_incoming_migration(QEMUFile *f)
{
    if (qemu_loadvm_state(f) < 0) {
        fprintf(stderr, "load of migration failed\n");
        exit(0);
    }
    qemu_announce_self();
    DPRINTF("successfully loaded vm state\n");
    if (autostart)
        vm_start();
}


void *av_realloc(void *ptr, unsigned int size)
{
#ifdef MEMALIGN_HACK
    //FIXME this isnt aligned correctly though it probably isnt needed
    int diff;
    if(!ptr) return av_malloc(size);
    diff= ((char*)ptr)[-1];
    return realloc(ptr - diff, size + diff) + diff;
#else
    return realloc(ptr, size);
#endif
}


static void init_excp_620 (CPUPPCState *env)

{

#if !defined(CONFIG_USER_ONLY)

    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;

    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;

    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;

    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;

    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;

    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;

    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;

    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;

    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;

    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;

    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;

    env->excp_vectors[POWERPC_EXCP_FPA]      = 0x00000E00;

    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;

    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;

    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;

    /* Hardware reset vector */

    env->hreset_vector = 0x0000000000000100ULL; /* ? */

#endif

}


int avpriv_dv_produce_packet(DVDemuxContext *c, AVPacket *pkt,

                             uint8_t *buf, int buf_size)

{

    int size, i;

    uint8_t *ppcm[4] = { 0 };

    if (buf_size < DV_PROFILE_BYTES ||

        !(c->sys = avpriv_dv_frame_profile(c->sys, buf, buf_size)) ||

        buf_size < c->sys->frame_size) {

        return -1;   /* Broken frame, or not enough data */

    }

    /* Queueing audio packet */

    /* FIXME: in case of no audio/bad audio we have to do something */

    size = dv_extract_audio_info(c, buf);

    for (i = 0; i < c->ach; i++) {

        c->audio_pkt[i].size = size;

        c->audio_pkt[i].pts  = c->abytes * 30000 * 8 /

                               c->ast[i]->codec->bit_rate;

        ppcm[i] = c->audio_buf[i];

    }

    if (c->ach)

        dv_extract_audio(buf, ppcm, c->sys);

    /* We work with 720p frames split in half, thus even frames have

     * channels 0,1 and odd 2,3. */

    if (c->sys->height == 720) {

        if (buf[1] & 0x0C) {

            c->audio_pkt[2].size = c->audio_pkt[3].size = 0;

        } else {

            c->audio_pkt[0].size = c->audio_pkt[1].size = 0;

            c->abytes           += size;

        }

    } else {

        c->abytes += size;

    }

    /* Now it's time to return video packet */

    size = dv_extract_video_info(c, buf);

    av_init_packet(pkt);

    pkt->data         = buf;

    pkt->size         = size;

    pkt->flags       |= AV_PKT_FLAG_KEY;

    pkt->stream_index = c->vst->index;

    pkt->pts          = c->frames;

    c->frames++;

    return size;

}


static void handle_event(int event)

{

    static bool logged;

    if (event & ~PVPANIC_PANICKED && !logged) {

        qemu_log_mask(LOG_GUEST_ERROR, "pvpanic: unknown event %#x.\n", event);

        logged = true;

    }

    if (event & PVPANIC_PANICKED) {

        panicked_mon_event("pause");

        vm_stop(RUN_STATE_GUEST_PANICKED);

        return;

    }

}


static void *iothread_run(void *opaque)

{

    IOThread *iothread = opaque;

    rcu_register_thread();

    my_iothread = iothread;

    qemu_mutex_lock(&iothread->init_done_lock);

    iothread->thread_id = qemu_get_thread_id();

    qemu_cond_signal(&iothread->init_done_cond);

    qemu_mutex_unlock(&iothread->init_done_lock);

    while (!atomic_read(&iothread->stopping)) {

        aio_poll(iothread->ctx, true);

        if (atomic_read(&iothread->worker_context)) {

            GMainLoop *loop;

            g_main_context_push_thread_default(iothread->worker_context);

            iothread->main_loop =

                g_main_loop_new(iothread->worker_context, TRUE);

            loop = iothread->main_loop;

            g_main_loop_run(iothread->main_loop);

            iothread->main_loop = NULL;

            g_main_loop_unref(loop);

            g_main_context_pop_thread_default(iothread->worker_context);

        }

    }

    rcu_unregister_thread();

    return NULL;

}


static void omap_rtc_write(void *opaque, hwaddr addr,

                           uint64_t value, unsigned size)

{

    struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;

    int offset = addr & OMAP_MPUI_REG_MASK;

    struct tm new_tm;

    time_t ti[2];

    if (size != 1) {

        return omap_badwidth_write8(opaque, addr, value);

    }

    switch (offset) {

    case 0x00:	/* SECONDS_REG */

#ifdef ALMDEBUG

        printf("RTC SEC_REG <-- %02x\n", value);

#endif

        s->ti -= s->current_tm.tm_sec;

        s->ti += from_bcd(value);

        return;

    case 0x04:	/* MINUTES_REG */

#ifdef ALMDEBUG

        printf("RTC MIN_REG <-- %02x\n", value);

#endif

        s->ti -= s->current_tm.tm_min * 60;

        s->ti += from_bcd(value) * 60;

        return;

    case 0x08:	/* HOURS_REG */

#ifdef ALMDEBUG

        printf("RTC HRS_REG <-- %02x\n", value);

#endif

        s->ti -= s->current_tm.tm_hour * 3600;

        if (s->pm_am) {

            s->ti += (from_bcd(value & 0x3f) & 12) * 3600;

            s->ti += ((value >> 7) & 1) * 43200;

        } else

            s->ti += from_bcd(value & 0x3f) * 3600;

        return;

    case 0x0c:	/* DAYS_REG */

#ifdef ALMDEBUG

        printf("RTC DAY_REG <-- %02x\n", value);

#endif

        s->ti -= s->current_tm.tm_mday * 86400;

        s->ti += from_bcd(value) * 86400;

        return;

    case 0x10:	/* MONTHS_REG */

#ifdef ALMDEBUG

        printf("RTC MTH_REG <-- %02x\n", value);

#endif

        memcpy(&new_tm, &s->current_tm, sizeof(new_tm));

        new_tm.tm_mon = from_bcd(value);

        ti[0] = mktimegm(&s->current_tm);

        ti[1] = mktimegm(&new_tm);

        if (ti[0] != -1 && ti[1] != -1) {

            s->ti -= ti[0];

            s->ti += ti[1];

        } else {

            /* A less accurate version */

            s->ti -= s->current_tm.tm_mon * 2592000;

            s->ti += from_bcd(value) * 2592000;

        }

        return;

    case 0x14:	/* YEARS_REG */

#ifdef ALMDEBUG

        printf("RTC YRS_REG <-- %02x\n", value);

#endif

        memcpy(&new_tm, &s->current_tm, sizeof(new_tm));

        new_tm.tm_year += from_bcd(value) - (new_tm.tm_year % 100);

        ti[0] = mktimegm(&s->current_tm);

        ti[1] = mktimegm(&new_tm);

        if (ti[0] != -1 && ti[1] != -1) {

            s->ti -= ti[0];

            s->ti += ti[1];

        } else {

            /* A less accurate version */

            s->ti -= (s->current_tm.tm_year % 100) * 31536000;

            s->ti += from_bcd(value) * 31536000;

        }

        return;

    case 0x18:	/* WEEK_REG */

        return;	/* Ignored */

    case 0x20:	/* ALARM_SECONDS_REG */

#ifdef ALMDEBUG

        printf("ALM SEC_REG <-- %02x\n", value);

#endif

        s->alarm_tm.tm_sec = from_bcd(value);

        omap_rtc_alarm_update(s);

        return;

    case 0x24:	/* ALARM_MINUTES_REG */

#ifdef ALMDEBUG

        printf("ALM MIN_REG <-- %02x\n", value);

#endif

        s->alarm_tm.tm_min = from_bcd(value);

        omap_rtc_alarm_update(s);

        return;

    case 0x28:	/* ALARM_HOURS_REG */

#ifdef ALMDEBUG

        printf("ALM HRS_REG <-- %02x\n", value);

#endif

        if (s->pm_am)

            s->alarm_tm.tm_hour =

                    ((from_bcd(value & 0x3f)) % 12) +

                    ((value >> 7) & 1) * 12;

        else

            s->alarm_tm.tm_hour = from_bcd(value);

        omap_rtc_alarm_update(s);

        return;

    case 0x2c:	/* ALARM_DAYS_REG */

#ifdef ALMDEBUG

        printf("ALM DAY_REG <-- %02x\n", value);

#endif

        s->alarm_tm.tm_mday = from_bcd(value);

        omap_rtc_alarm_update(s);

        return;

    case 0x30:	/* ALARM_MONTHS_REG */

#ifdef ALMDEBUG

        printf("ALM MON_REG <-- %02x\n", value);

#endif

        s->alarm_tm.tm_mon = from_bcd(value);

        omap_rtc_alarm_update(s);

        return;

    case 0x34:	/* ALARM_YEARS_REG */

#ifdef ALMDEBUG

        printf("ALM YRS_REG <-- %02x\n", value);

#endif

        s->alarm_tm.tm_year = from_bcd(value);

        omap_rtc_alarm_update(s);

        return;

    case 0x40:	/* RTC_CTRL_REG */

#ifdef ALMDEBUG

        printf("RTC CONTROL <-- %02x\n", value);

#endif

        s->pm_am = (value >> 3) & 1;

        s->auto_comp = (value >> 2) & 1;

        s->round = (value >> 1) & 1;

        s->running = value & 1;

        s->status &= 0xfd;

        s->status |= s->running << 1;

        return;

    case 0x44:	/* RTC_STATUS_REG */

#ifdef ALMDEBUG

        printf("RTC STATUSL <-- %02x\n", value);

#endif

        s->status &= ~((value & 0xc0) ^ 0x80);

        omap_rtc_interrupts_update(s);

        return;

    case 0x48:	/* RTC_INTERRUPTS_REG */

#ifdef ALMDEBUG

        printf("RTC INTRS <-- %02x\n", value);

#endif

        s->interrupts = value;

        return;

    case 0x4c:	/* RTC_COMP_LSB_REG */

#ifdef ALMDEBUG

        printf("RTC COMPLSB <-- %02x\n", value);

#endif

        s->comp_reg &= 0xff00;

        s->comp_reg |= 0x00ff & value;

        return;

    case 0x50:	/* RTC_COMP_MSB_REG */

#ifdef ALMDEBUG

        printf("RTC COMPMSB <-- %02x\n", value);

#endif

        s->comp_reg &= 0x00ff;

        s->comp_reg |= 0xff00 & (value << 8);

        return;

    default:

        OMAP_BAD_REG(addr);

        return;

    }

}


static void neon_store_reg(int reg, int pass, TCGv var)

{

    tcg_gen_st_i32(var, cpu_env, neon_reg_offset(reg, pass));

    dead_tmp(var);

}