static int thp_read_packet(AVFormatContext *s,

                            AVPacket *pkt)

{

    ThpDemuxContext *thp = s->priv_data;

    AVIOContext *pb = s->pb;

    unsigned int size;

    int ret;

    if (thp->audiosize == 0) {

        /* Terminate when last frame is reached.  */

        if (thp->frame >= thp->framecnt)

            return AVERROR_EOF;

        avio_seek(pb, thp->next_frame, SEEK_SET);

        /* Locate the next frame and read out its size.  */

        thp->next_frame += FFMAX(thp->next_framesz, 1);

        thp->next_framesz = avio_rb32(pb);

                        avio_rb32(pb); /* Previous total size.  */

        size          = avio_rb32(pb); /* Total size of this frame.  */

        /* Store the audiosize so the next time this function is called,

           the audio can be read.  */

        if (thp->has_audio)

            thp->audiosize = avio_rb32(pb); /* Audio size.  */

        else

            thp->frame++;

        ret = av_get_packet(pb, pkt, size);

        if (ret != size) {

            av_free_packet(pkt);

            return AVERROR(EIO);

        }

        pkt->stream_index = thp->video_stream_index;

    } else {

        ret = av_get_packet(pb, pkt, thp->audiosize);

        if (ret != thp->audiosize) {

            av_free_packet(pkt);

            return AVERROR(EIO);

        }

        pkt->stream_index = thp->audio_stream_index;

        if (thp->audiosize >= 8)

            pkt->duration = AV_RB32(&pkt->data[4]);

        thp->audiosize = 0;

        thp->frame++;

    }

    return 0;

}


static int RENAME(resample_common)(ResampleContext *c,

                                   DELEM *dst, const DELEM *src,

                                   int n, int update_ctx)

{

    int dst_index;

    int index= c->index;

    int frac= c->frac;

    int sample_index = index >> c->phase_shift;

    index &= c->phase_mask;

    for (dst_index = 0; dst_index < n; dst_index++) {

        FELEM *filter = ((FELEM *) c->filter_bank) + c->filter_alloc * index;

        FELEM2 val=0;

        int i;

        for (i = 0; i < c->filter_length; i++) {

            val += src[sample_index + i] * (FELEM2)filter[i];

        }

        OUT(dst[dst_index], val);

        frac  += c->dst_incr_mod;

        index += c->dst_incr_div;

        if (frac >= c->src_incr) {

            frac -= c->src_incr;

            index++;

        }

        sample_index += index >> c->phase_shift;

        index &= c->phase_mask;

    }

    if(update_ctx){

        c->frac= frac;

        c->index= index;

    }

    return sample_index;

}


static int send_status(int sockfd, struct iovec *iovec, int status)

{

    ProxyHeader header;

    int retval, msg_size;

    if (status < 0) {

        header.type = T_ERROR;

    } else {

        header.type = T_SUCCESS;

    header.size = sizeof(status);

    /*

     * marshal the return status. We don't check error.

     * because we are sure we have enough space for the status

     */

    msg_size = proxy_marshal(iovec, 0, "ddd", header.type,

                             header.size, status);

    retval = socket_write(sockfd, iovec->iov_base, msg_size);

    if (retval < 0) {

        return retval;

    return 0;


int av_image_fill_pointers(uint8_t *data[4], enum PixelFormat pix_fmt, int height,

                           uint8_t *ptr, const int linesizes[4])

{

    int i, total_size, size[4], has_plane[4];

    const AVPixFmtDescriptor *desc = &av_pix_fmt_descriptors[pix_fmt];

    memset(data     , 0, sizeof(data[0])*4);

    memset(size     , 0, sizeof(size));

    memset(has_plane, 0, sizeof(has_plane));

    if ((unsigned)pix_fmt >= PIX_FMT_NB || desc->flags & PIX_FMT_HWACCEL)

        return AVERROR(EINVAL);

    data[0] = ptr;

    if (linesizes[0] > (INT_MAX - 1024) / height)

        return AVERROR(EINVAL);

    size[0] = linesizes[0] * height;

    if (desc->flags & PIX_FMT_PAL) {

        size[0] = (size[0] + 3) & ~3;

        data[1] = ptr + size[0]; /* palette is stored here as 256 32 bits words */

        return size[0] + 256 * 4;

    }

    for (i = 0; i < 4; i++)

        has_plane[desc->comp[i].plane] = 1;

    total_size = size[0];

    for (i = 1; i < 4 && has_plane[i]; i++) {

        int h, s = (i == 1 || i == 2) ? desc->log2_chroma_h : 0;

        data[i] = data[i-1] + size[i-1];

        h = (height + (1 << s) - 1) >> s;

        if (linesizes[i] > INT_MAX / h)

            return AVERROR(EINVAL);

        size[i] = h * linesizes[i];

        if (total_size > INT_MAX - size[i])

            return AVERROR(EINVAL);

        total_size += size[i];

    }

    return total_size;

}


int64_t qmp_query_migrate_cache_size(Error **errp)

{

    return migrate_xbzrle_cache_size();

}


av_cold int MPV_common_init(MpegEncContext *s)

{

    int y_size, c_size, yc_size, i, mb_array_size, mv_table_size, x, y, threads;

    if(s->codec_id == CODEC_ID_MPEG2VIDEO && !s->progressive_sequence)

        s->mb_height = (s->height + 31) / 32 * 2;

    else

        s->mb_height = (s->height + 15) / 16;

    if(s->avctx->pix_fmt == PIX_FMT_NONE){

        av_log(s->avctx, AV_LOG_ERROR, "decoding to PIX_FMT_NONE is not supported.\n");

        return -1;

    }

    if(s->avctx->thread_count > MAX_THREADS || (s->avctx->thread_count > s->mb_height && s->mb_height)){

        av_log(s->avctx, AV_LOG_ERROR, "too many threads\n");

        return -1;

    }

    if((s->width || s->height) && avcodec_check_dimensions(s->avctx, s->width, s->height))

        return -1;

    dsputil_init(&s->dsp, s->avctx);

    ff_dct_common_init(s);

    s->flags= s->avctx->flags;

    s->flags2= s->avctx->flags2;

    s->mb_width  = (s->width  + 15) / 16;

    s->mb_stride = s->mb_width + 1;

    s->b8_stride = s->mb_width*2 + 1;

    s->b4_stride = s->mb_width*4 + 1;

    mb_array_size= s->mb_height * s->mb_stride;

    mv_table_size= (s->mb_height+2) * s->mb_stride + 1;

    /* set chroma shifts */

    avcodec_get_chroma_sub_sample(s->avctx->pix_fmt,&(s->chroma_x_shift),

                                                    &(s->chroma_y_shift) );

    /* set default edge pos, will be overriden in decode_header if needed */

    s->h_edge_pos= s->mb_width*16;

    s->v_edge_pos= s->mb_height*16;

    s->mb_num = s->mb_width * s->mb_height;

    s->block_wrap[0]=

    s->block_wrap[1]=

    s->block_wrap[2]=

    s->block_wrap[3]= s->b8_stride;

    s->block_wrap[4]=

    s->block_wrap[5]= s->mb_stride;

    y_size = s->b8_stride * (2 * s->mb_height + 1);

    c_size = s->mb_stride * (s->mb_height + 1);

    yc_size = y_size + 2 * c_size;

    /* convert fourcc to upper case */

    s->codec_tag = ff_toupper4(s->avctx->codec_tag);

    s->stream_codec_tag = ff_toupper4(s->avctx->stream_codec_tag);

    s->avctx->coded_frame= (AVFrame*)&s->current_picture;

    FF_ALLOCZ_OR_GOTO(s->avctx, s->mb_index2xy, (s->mb_num+1)*sizeof(int), fail) //error ressilience code looks cleaner with this

    for(y=0; y<s->mb_height; y++){

        for(x=0; x<s->mb_width; x++){

            s->mb_index2xy[ x + y*s->mb_width ] = x + y*s->mb_stride;

        }

    }

    s->mb_index2xy[ s->mb_height*s->mb_width ] = (s->mb_height-1)*s->mb_stride + s->mb_width; //FIXME really needed?

    if (s->encoding) {

        /* Allocate MV tables */

        FF_ALLOCZ_OR_GOTO(s->avctx, s->p_mv_table_base            , mv_table_size * 2 * sizeof(int16_t), fail)

        FF_ALLOCZ_OR_GOTO(s->avctx, s->b_forw_mv_table_base       , mv_table_size * 2 * sizeof(int16_t), fail)

        FF_ALLOCZ_OR_GOTO(s->avctx, s->b_back_mv_table_base       , mv_table_size * 2 * sizeof(int16_t), fail)

        FF_ALLOCZ_OR_GOTO(s->avctx, s->b_bidir_forw_mv_table_base , mv_table_size * 2 * sizeof(int16_t), fail)

        FF_ALLOCZ_OR_GOTO(s->avctx, s->b_bidir_back_mv_table_base , mv_table_size * 2 * sizeof(int16_t), fail)

        FF_ALLOCZ_OR_GOTO(s->avctx, s->b_direct_mv_table_base     , mv_table_size * 2 * sizeof(int16_t), fail)

        s->p_mv_table           = s->p_mv_table_base            + s->mb_stride + 1;

        s->b_forw_mv_table      = s->b_forw_mv_table_base       + s->mb_stride + 1;

        s->b_back_mv_table      = s->b_back_mv_table_base       + s->mb_stride + 1;

        s->b_bidir_forw_mv_table= s->b_bidir_forw_mv_table_base + s->mb_stride + 1;

        s->b_bidir_back_mv_table= s->b_bidir_back_mv_table_base + s->mb_stride + 1;

        s->b_direct_mv_table    = s->b_direct_mv_table_base     + s->mb_stride + 1;

        if(s->msmpeg4_version){

            FF_ALLOCZ_OR_GOTO(s->avctx, s->ac_stats, 2*2*(MAX_LEVEL+1)*(MAX_RUN+1)*2*sizeof(int), fail);

        }

        FF_ALLOCZ_OR_GOTO(s->avctx, s->avctx->stats_out, 256, fail);

        /* Allocate MB type table */

        FF_ALLOCZ_OR_GOTO(s->avctx, s->mb_type  , mb_array_size * sizeof(uint16_t), fail) //needed for encoding

        FF_ALLOCZ_OR_GOTO(s->avctx, s->lambda_table, mb_array_size * sizeof(int), fail)

        FF_ALLOCZ_OR_GOTO(s->avctx, s->q_intra_matrix  , 64*32   * sizeof(int), fail)

        FF_ALLOCZ_OR_GOTO(s->avctx, s->q_inter_matrix  , 64*32   * sizeof(int), fail)

        FF_ALLOCZ_OR_GOTO(s->avctx, s->q_intra_matrix16, 64*32*2 * sizeof(uint16_t), fail)

        FF_ALLOCZ_OR_GOTO(s->avctx, s->q_inter_matrix16, 64*32*2 * sizeof(uint16_t), fail)

        FF_ALLOCZ_OR_GOTO(s->avctx, s->input_picture, MAX_PICTURE_COUNT * sizeof(Picture*), fail)

        FF_ALLOCZ_OR_GOTO(s->avctx, s->reordered_input_picture, MAX_PICTURE_COUNT * sizeof(Picture*), fail)

        if(s->avctx->noise_reduction){

            FF_ALLOCZ_OR_GOTO(s->avctx, s->dct_offset, 2 * 64 * sizeof(uint16_t), fail)

        }

    }

    FF_ALLOCZ_OR_GOTO(s->avctx, s->picture, MAX_PICTURE_COUNT * sizeof(Picture), fail)

    for(i = 0; i < MAX_PICTURE_COUNT; i++) {

        avcodec_get_frame_defaults((AVFrame *)&s->picture[i]);

    }

    FF_ALLOCZ_OR_GOTO(s->avctx, s->error_status_table, mb_array_size*sizeof(uint8_t), fail)

    if(s->codec_id==CODEC_ID_MPEG4 || (s->flags & CODEC_FLAG_INTERLACED_ME)){

        /* interlaced direct mode decoding tables */

            for(i=0; i<2; i++){

                int j, k;

                for(j=0; j<2; j++){

                    for(k=0; k<2; k++){

                        FF_ALLOCZ_OR_GOTO(s->avctx,    s->b_field_mv_table_base[i][j][k], mv_table_size * 2 * sizeof(int16_t), fail)

                        s->b_field_mv_table[i][j][k] = s->b_field_mv_table_base[i][j][k] + s->mb_stride + 1;

                    }

                    FF_ALLOCZ_OR_GOTO(s->avctx, s->b_field_select_table [i][j], mb_array_size * 2 * sizeof(uint8_t), fail)

                    FF_ALLOCZ_OR_GOTO(s->avctx, s->p_field_mv_table_base[i][j], mv_table_size * 2 * sizeof(int16_t), fail)

                    s->p_field_mv_table[i][j] = s->p_field_mv_table_base[i][j]+ s->mb_stride + 1;

                }

                FF_ALLOCZ_OR_GOTO(s->avctx, s->p_field_select_table[i], mb_array_size * 2 * sizeof(uint8_t), fail)

            }

    }

    if (s->out_format == FMT_H263) {

        /* ac values */

        FF_ALLOCZ_OR_GOTO(s->avctx, s->ac_val_base, yc_size * sizeof(int16_t) * 16, fail);

        s->ac_val[0] = s->ac_val_base + s->b8_stride + 1;

        s->ac_val[1] = s->ac_val_base + y_size + s->mb_stride + 1;

        s->ac_val[2] = s->ac_val[1] + c_size;

        /* cbp values */

        FF_ALLOCZ_OR_GOTO(s->avctx, s->coded_block_base, y_size, fail);

        s->coded_block= s->coded_block_base + s->b8_stride + 1;

        /* cbp, ac_pred, pred_dir */

        FF_ALLOCZ_OR_GOTO(s->avctx, s->cbp_table     , mb_array_size * sizeof(uint8_t), fail)

        FF_ALLOCZ_OR_GOTO(s->avctx, s->pred_dir_table, mb_array_size * sizeof(uint8_t), fail)

    }

    if (s->h263_pred || s->h263_plus || !s->encoding) {

        /* dc values */

        //MN: we need these for error resilience of intra-frames

        FF_ALLOCZ_OR_GOTO(s->avctx, s->dc_val_base, yc_size * sizeof(int16_t), fail);

        s->dc_val[0] = s->dc_val_base + s->b8_stride + 1;

        s->dc_val[1] = s->dc_val_base + y_size + s->mb_stride + 1;

        s->dc_val[2] = s->dc_val[1] + c_size;

        for(i=0;i<yc_size;i++)

            s->dc_val_base[i] = 1024;

    }

    /* which mb is a intra block */

    FF_ALLOCZ_OR_GOTO(s->avctx, s->mbintra_table, mb_array_size, fail);

    memset(s->mbintra_table, 1, mb_array_size);

    /* init macroblock skip table */

    FF_ALLOCZ_OR_GOTO(s->avctx, s->mbskip_table, mb_array_size+2, fail);

    //Note the +1 is for a quicker mpeg4 slice_end detection

    FF_ALLOCZ_OR_GOTO(s->avctx, s->prev_pict_types, PREV_PICT_TYPES_BUFFER_SIZE, fail);

    s->parse_context.state= -1;

    if((s->avctx->debug&(FF_DEBUG_VIS_QP|FF_DEBUG_VIS_MB_TYPE)) || (s->avctx->debug_mv)){

       s->visualization_buffer[0] = av_malloc((s->mb_width*16 + 2*EDGE_WIDTH) * s->mb_height*16 + 2*EDGE_WIDTH);

       s->visualization_buffer[1] = av_malloc((s->mb_width*16 + 2*EDGE_WIDTH) * s->mb_height*16 + 2*EDGE_WIDTH);

       s->visualization_buffer[2] = av_malloc((s->mb_width*16 + 2*EDGE_WIDTH) * s->mb_height*16 + 2*EDGE_WIDTH);

    }

    s->context_initialized = 1;

    s->thread_context[0]= s;

    threads = s->avctx->thread_count;

    for(i=1; i<threads; i++){

        s->thread_context[i]= av_malloc(sizeof(MpegEncContext));

        memcpy(s->thread_context[i], s, sizeof(MpegEncContext));

    }

    for(i=0; i<threads; i++){

        if(init_duplicate_context(s->thread_context[i], s) < 0)

           goto fail;

        s->thread_context[i]->start_mb_y= (s->mb_height*(i  ) + s->avctx->thread_count/2) / s->avctx->thread_count;

        s->thread_context[i]->end_mb_y  = (s->mb_height*(i+1) + s->avctx->thread_count/2) / s->avctx->thread_count;

    }

    return 0;

 fail:

    MPV_common_end(s);

    return -1;

}


static av_cold int aac_decode_init(AVCodecContext *avctx)

{

    AACContext *ac = avctx->priv_data;

    int ret;

    ac->avctx = avctx;

    ac->oc[1].m4ac.sample_rate = avctx->sample_rate;

    aacdec_init(ac);

#if USE_FIXED

    avctx->sample_fmt = AV_SAMPLE_FMT_S32P;

#else

    avctx->sample_fmt = AV_SAMPLE_FMT_FLTP;

#endif /* USE_FIXED */

    if (avctx->extradata_size > 0) {

        if ((ret = decode_audio_specific_config(ac, ac->avctx, &ac->oc[1].m4ac,

                                                avctx->extradata,

                                                avctx->extradata_size * 8,

                                                1)) < 0)

            return ret;

    } else {

        int sr, i;

        uint8_t layout_map[MAX_ELEM_ID*4][3];

        int layout_map_tags;

        sr = sample_rate_idx(avctx->sample_rate);

        ac->oc[1].m4ac.sampling_index = sr;

        ac->oc[1].m4ac.channels = avctx->channels;

        ac->oc[1].m4ac.sbr = -1;

        ac->oc[1].m4ac.ps = -1;

        for (i = 0; i < FF_ARRAY_ELEMS(ff_mpeg4audio_channels); i++)

            if (ff_mpeg4audio_channels[i] == avctx->channels)

                break;

        if (i == FF_ARRAY_ELEMS(ff_mpeg4audio_channels)) {

            i = 0;

        }

        ac->oc[1].m4ac.chan_config = i;

        if (ac->oc[1].m4ac.chan_config) {

            int ret = set_default_channel_config(avctx, layout_map,

                &layout_map_tags, ac->oc[1].m4ac.chan_config);

            if (!ret)

                output_configure(ac, layout_map, layout_map_tags,

                                 OC_GLOBAL_HDR, 0);

            else if (avctx->err_recognition & AV_EF_EXPLODE)

                return AVERROR_INVALIDDATA;

        }

    }

    if (avctx->channels > MAX_CHANNELS) {

        av_log(avctx, AV_LOG_ERROR, "Too many channels\n");

        return AVERROR_INVALIDDATA;

    }

    AAC_INIT_VLC_STATIC( 0, 304);

    AAC_INIT_VLC_STATIC( 1, 270);

    AAC_INIT_VLC_STATIC( 2, 550);

    AAC_INIT_VLC_STATIC( 3, 300);

    AAC_INIT_VLC_STATIC( 4, 328);

    AAC_INIT_VLC_STATIC( 5, 294);

    AAC_INIT_VLC_STATIC( 6, 306);

    AAC_INIT_VLC_STATIC( 7, 268);

    AAC_INIT_VLC_STATIC( 8, 510);

    AAC_INIT_VLC_STATIC( 9, 366);

    AAC_INIT_VLC_STATIC(10, 462);

    AAC_RENAME(ff_aac_sbr_init)();

#if USE_FIXED

    ac->fdsp = avpriv_alloc_fixed_dsp(avctx->flags & AV_CODEC_FLAG_BITEXACT);

#else

    ac->fdsp = avpriv_float_dsp_alloc(avctx->flags & AV_CODEC_FLAG_BITEXACT);

#endif /* USE_FIXED */

    if (!ac->fdsp) {

        return AVERROR(ENOMEM);

    }

    ac->random_state = 0x1f2e3d4c;

    ff_aac_tableinit();

    INIT_VLC_STATIC(&vlc_scalefactors, 7,

                    FF_ARRAY_ELEMS(ff_aac_scalefactor_code),

                    ff_aac_scalefactor_bits,

                    sizeof(ff_aac_scalefactor_bits[0]),

                    sizeof(ff_aac_scalefactor_bits[0]),

                    ff_aac_scalefactor_code,

                    sizeof(ff_aac_scalefactor_code[0]),

                    sizeof(ff_aac_scalefactor_code[0]),

                    352);

    AAC_RENAME_32(ff_mdct_init)(&ac->mdct,       11, 1, 1.0 / RANGE15(1024.0));

    AAC_RENAME_32(ff_mdct_init)(&ac->mdct_ld,    10, 1, 1.0 / RANGE15(512.0));

    AAC_RENAME_32(ff_mdct_init)(&ac->mdct_small,  8, 1, 1.0 / RANGE15(128.0));

    AAC_RENAME_32(ff_mdct_init)(&ac->mdct_ltp,   11, 0, RANGE15(-2.0));

#if !USE_FIXED

    ret = ff_imdct15_init(&ac->mdct480, 5);

    if (ret < 0)

        return ret;

#endif

    // window initialization

    AAC_RENAME(ff_kbd_window_init)(AAC_RENAME(ff_aac_kbd_long_1024), 4.0, 1024);

    AAC_RENAME(ff_kbd_window_init)(AAC_RENAME(ff_aac_kbd_short_128), 6.0, 128);

    AAC_RENAME(ff_init_ff_sine_windows)(10);

    AAC_RENAME(ff_init_ff_sine_windows)( 9);

    AAC_RENAME(ff_init_ff_sine_windows)( 7);

    AAC_RENAME(cbrt_tableinit)();

    return 0;

}


PPC_OP(addic)

{

    T1 = T0;

    T0 += PARAM(1);

    if (T0 < T1) {

        xer_ca = 1;

    } else {

        xer_ca = 0;

    }

    RETURN();

}


void qemu_update_position(QEMUFile *f, size_t size)

{

    f->pos += size;

}


static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)

{

    int32_t disp21, disp16, disp12 __attribute__((unused));

    uint16_t fn11;

    uint8_t opc, ra, rb, rc, fpfn, fn7, lit;

    bool islit;

    TCGv va, vb, vc, tmp;

    TCGv_i32 t32;

    ExitStatus ret;

    /* Decode all instruction fields */

    opc = extract32(insn, 26, 6);

    ra = extract32(insn, 21, 5);

    rb = extract32(insn, 16, 5);

    rc = extract32(insn, 0, 5);

    islit = extract32(insn, 12, 1);

    lit = extract32(insn, 13, 8);

    disp21 = sextract32(insn, 0, 21);

    disp16 = sextract32(insn, 0, 16);

    disp12 = sextract32(insn, 0, 12);

    fn11 = extract32(insn, 5, 11);

    fpfn = extract32(insn, 5, 6);

    fn7 = extract32(insn, 5, 7);

    if (rb == 31 && !islit) {

        islit = true;

        lit = 0;

    }

    ret = NO_EXIT;

    switch (opc) {

    case 0x00:

        /* CALL_PAL */

        ret = gen_call_pal(ctx, insn & 0x03ffffff);

        break;

    case 0x01:

        /* OPC01 */

        goto invalid_opc;

    case 0x02:

        /* OPC02 */

        goto invalid_opc;

    case 0x03:

        /* OPC03 */

        goto invalid_opc;

    case 0x04:

        /* OPC04 */

        goto invalid_opc;

    case 0x05:

        /* OPC05 */

        goto invalid_opc;

    case 0x06:

        /* OPC06 */

        goto invalid_opc;

    case 0x07:

        /* OPC07 */

        goto invalid_opc;

    case 0x09:

        /* LDAH */

        disp16 = (uint32_t)disp16 << 16;

        /* fall through */

    case 0x08:

        /* LDA */

        va = dest_gpr(ctx, ra);

        /* It's worth special-casing immediate loads.  */

        if (rb == 31) {

            tcg_gen_movi_i64(va, disp16);

        } else {

            tcg_gen_addi_i64(va, load_gpr(ctx, rb), disp16);

        }

        break;

    case 0x0A:

        /* LDBU */

        REQUIRE_TB_FLAG(TB_FLAGS_AMASK_BWX);

        gen_load_mem(ctx, &tcg_gen_qemu_ld8u, ra, rb, disp16, 0, 0);

        break;

    case 0x0B:

        /* LDQ_U */

        gen_load_mem(ctx, &tcg_gen_qemu_ld64, ra, rb, disp16, 0, 1);

        break;

    case 0x0C:

        /* LDWU */

        REQUIRE_TB_FLAG(TB_FLAGS_AMASK_BWX);

        gen_load_mem(ctx, &tcg_gen_qemu_ld16u, ra, rb, disp16, 0, 0);

        break;

    case 0x0D:

        /* STW */

        REQUIRE_TB_FLAG(TB_FLAGS_AMASK_BWX);

        gen_store_mem(ctx, &tcg_gen_qemu_st16, ra, rb, disp16, 0, 0);

        break;

    case 0x0E:

        /* STB */

        REQUIRE_TB_FLAG(TB_FLAGS_AMASK_BWX);

        gen_store_mem(ctx, &tcg_gen_qemu_st8, ra, rb, disp16, 0, 0);

        break;

    case 0x0F:

        /* STQ_U */

        gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 0, 1);

        break;

    case 0x10:

        vc = dest_gpr(ctx, rc);

        vb = load_gpr_lit(ctx, rb, lit, islit);

        if (ra == 31) {

            if (fn7 == 0x00) {

                /* Special case ADDL as SEXTL.  */

                tcg_gen_ext32s_i64(vc, vb);

                break;

            }

            if (fn7 == 0x29) {

                /* Special case SUBQ as NEGQ.  */

                tcg_gen_neg_i64(vc, vb);

                break;

            }

        }

        va = load_gpr(ctx, ra);

        switch (fn7) {

        case 0x00:

            /* ADDL */

            tcg_gen_add_i64(vc, va, vb);

            tcg_gen_ext32s_i64(vc, vc);

            break;

        case 0x02:

            /* S4ADDL */

            tmp = tcg_temp_new();

            tcg_gen_shli_i64(tmp, va, 2);

            tcg_gen_add_i64(tmp, tmp, vb);

            tcg_gen_ext32s_i64(vc, tmp);

            tcg_temp_free(tmp);

            break;

        case 0x09:

            /* SUBL */

            tcg_gen_sub_i64(vc, va, vb);

            tcg_gen_ext32s_i64(vc, vc);

            break;

        case 0x0B:

            /* S4SUBL */

            tmp = tcg_temp_new();

            tcg_gen_shli_i64(tmp, va, 2);

            tcg_gen_sub_i64(tmp, tmp, vb);

            tcg_gen_ext32s_i64(vc, tmp);

            tcg_temp_free(tmp);

            break;

        case 0x0F:

            /* CMPBGE */

            gen_helper_cmpbge(vc, va, vb);

            break;

        case 0x12:

            /* S8ADDL */

            tmp = tcg_temp_new();

            tcg_gen_shli_i64(tmp, va, 3);

            tcg_gen_add_i64(tmp, tmp, vb);

            tcg_gen_ext32s_i64(vc, tmp);

            tcg_temp_free(tmp);

            break;

        case 0x1B:

            /* S8SUBL */

            tmp = tcg_temp_new();

            tcg_gen_shli_i64(tmp, va, 3);

            tcg_gen_sub_i64(tmp, tmp, vb);

            tcg_gen_ext32s_i64(vc, tmp);

            tcg_temp_free(tmp);

            break;

        case 0x1D:

            /* CMPULT */

            tcg_gen_setcond_i64(TCG_COND_LTU, vc, va, vb);

            break;

        case 0x20:

            /* ADDQ */

            tcg_gen_add_i64(vc, va, vb);

            break;

        case 0x22:

            /* S4ADDQ */

            tmp = tcg_temp_new();

            tcg_gen_shli_i64(tmp, va, 2);

            tcg_gen_add_i64(vc, tmp, vb);

            tcg_temp_free(tmp);

            break;

        case 0x29:

            /* SUBQ */

            tcg_gen_sub_i64(vc, va, vb);

            break;

        case 0x2B:

            /* S4SUBQ */

            tmp = tcg_temp_new();

            tcg_gen_shli_i64(tmp, va, 2);

            tcg_gen_sub_i64(vc, tmp, vb);

            tcg_temp_free(tmp);

            break;

        case 0x2D:

            /* CMPEQ */

            tcg_gen_setcond_i64(TCG_COND_EQ, vc, va, vb);

            break;

        case 0x32:

            /* S8ADDQ */

            tmp = tcg_temp_new();

            tcg_gen_shli_i64(tmp, va, 3);

            tcg_gen_add_i64(vc, tmp, vb);

            tcg_temp_free(tmp);

            break;

        case 0x3B:

            /* S8SUBQ */

            tmp = tcg_temp_new();

            tcg_gen_shli_i64(tmp, va, 3);

            tcg_gen_sub_i64(vc, tmp, vb);

            tcg_temp_free(tmp);

            break;

        case 0x3D:

            /* CMPULE */

            tcg_gen_setcond_i64(TCG_COND_LEU, vc, va, vb);

            break;

        case 0x40:

            /* ADDL/V */

            gen_helper_addlv(vc, cpu_env, va, vb);

            break;

        case 0x49:

            /* SUBL/V */

            gen_helper_sublv(vc, cpu_env, va, vb);

            break;

        case 0x4D:

            /* CMPLT */

            tcg_gen_setcond_i64(TCG_COND_LT, vc, va, vb);

            break;

        case 0x60:

            /* ADDQ/V */

            gen_helper_addqv(vc, cpu_env, va, vb);

            break;

        case 0x69:

            /* SUBQ/V */

            gen_helper_subqv(vc, cpu_env, va, vb);

            break;

        case 0x6D:

            /* CMPLE */

            tcg_gen_setcond_i64(TCG_COND_LE, vc, va, vb);

            break;

        default:

            goto invalid_opc;

        }

        break;

    case 0x11:

        if (fn7 == 0x20) {

            if (rc == 31) {

                /* Special case BIS as NOP.  */

                break;

            }

            if (ra == 31) {

                /* Special case BIS as MOV.  */

                vc = dest_gpr(ctx, rc);

                if (islit) {

                    tcg_gen_movi_i64(vc, lit);

                } else {

                    tcg_gen_mov_i64(vc, load_gpr(ctx, rb));

                }

                break;

            }

        }

        vc = dest_gpr(ctx, rc);

        vb = load_gpr_lit(ctx, rb, lit, islit);

        if (fn7 == 0x28 && ra == 31) {

            /* Special case ORNOT as NOT.  */

            tcg_gen_not_i64(vc, vb);

            break;

        }

        va = load_gpr(ctx, ra);

        switch (fn7) {

        case 0x00:

            /* AND */

            tcg_gen_and_i64(vc, va, vb);

            break;

        case 0x08:

            /* BIC */

            tcg_gen_andc_i64(vc, va, vb);

            break;

        case 0x14:

            /* CMOVLBS */

            tmp = tcg_temp_new();

            tcg_gen_andi_i64(tmp, va, 1);

            tcg_gen_movcond_i64(TCG_COND_NE, vc, tmp, load_zero(ctx),

                                vb, load_gpr(ctx, rc));

            tcg_temp_free(tmp);

            break;

        case 0x16:

            /* CMOVLBC */

            tmp = tcg_temp_new();

            tcg_gen_andi_i64(tmp, va, 1);

            tcg_gen_movcond_i64(TCG_COND_EQ, vc, tmp, load_zero(ctx),

                                vb, load_gpr(ctx, rc));

            tcg_temp_free(tmp);

            break;

        case 0x20:

            /* BIS */

            tcg_gen_or_i64(vc, va, vb);

            break;

        case 0x24:

            /* CMOVEQ */

            tcg_gen_movcond_i64(TCG_COND_EQ, vc, va, load_zero(ctx),

                                vb, load_gpr(ctx, rc));

            break;

        case 0x26:

            /* CMOVNE */

            tcg_gen_movcond_i64(TCG_COND_NE, vc, va, load_zero(ctx),

                                vb, load_gpr(ctx, rc));

            break;

        case 0x28:

            /* ORNOT */

            tcg_gen_orc_i64(vc, va, vb);

            break;

        case 0x40:

            /* XOR */

            tcg_gen_xor_i64(vc, va, vb);

            break;

        case 0x44:

            /* CMOVLT */

            tcg_gen_movcond_i64(TCG_COND_LT, vc, va, load_zero(ctx),

                                vb, load_gpr(ctx, rc));

            break;

        case 0x46:

            /* CMOVGE */

            tcg_gen_movcond_i64(TCG_COND_GE, vc, va, load_zero(ctx),

                                vb, load_gpr(ctx, rc));

            break;

        case 0x48:

            /* EQV */

            tcg_gen_eqv_i64(vc, va, vb);

            break;

        case 0x61:

            /* AMASK */

            REQUIRE_REG_31(ra);

            {

                uint64_t amask = ctx->tb->flags >> TB_FLAGS_AMASK_SHIFT;

                tcg_gen_andi_i64(vc, vb, ~amask);

            }

            break;

        case 0x64:

            /* CMOVLE */

            tcg_gen_movcond_i64(TCG_COND_LE, vc, va, load_zero(ctx),

                                vb, load_gpr(ctx, rc));

            break;

        case 0x66:

            /* CMOVGT */

            tcg_gen_movcond_i64(TCG_COND_GT, vc, va, load_zero(ctx),

                                vb, load_gpr(ctx, rc));

            break;

        case 0x6C:

            /* IMPLVER */

            REQUIRE_REG_31(ra);

            tcg_gen_movi_i64(vc, ctx->implver);

            break;

        default:

            goto invalid_opc;

        }

        break;

    case 0x12:

        vc = dest_gpr(ctx, rc);

        va = load_gpr(ctx, ra);

        switch (fn7) {

        case 0x02:

            /* MSKBL */

            gen_msk_l(ctx, vc, va, rb, islit, lit, 0x01);

            break;

        case 0x06:

            /* EXTBL */

            gen_ext_l(ctx, vc, va, rb, islit, lit, 0x01);

            break;

        case 0x0B:

            /* INSBL */

            gen_ins_l(ctx, vc, va, rb, islit, lit, 0x01);

            break;

        case 0x12:

            /* MSKWL */

            gen_msk_l(ctx, vc, va, rb, islit, lit, 0x03);

            break;

        case 0x16:

            /* EXTWL */

            gen_ext_l(ctx, vc, va, rb, islit, lit, 0x03);

            break;

        case 0x1B:

            /* INSWL */

            gen_ins_l(ctx, vc, va, rb, islit, lit, 0x03);

            break;

        case 0x22:

            /* MSKLL */

            gen_msk_l(ctx, vc, va, rb, islit, lit, 0x0f);

            break;

        case 0x26:

            /* EXTLL */

            gen_ext_l(ctx, vc, va, rb, islit, lit, 0x0f);

            break;

        case 0x2B:

            /* INSLL */

            gen_ins_l(ctx, vc, va, rb, islit, lit, 0x0f);

            break;

        case 0x30:

            /* ZAP */

            if (islit) {

                gen_zapnoti(vc, va, ~lit);

            } else {

                gen_helper_zap(vc, va, load_gpr(ctx, rb));

            }

            break;

        case 0x31:

            /* ZAPNOT */

            if (islit) {

                gen_zapnoti(vc, va, lit);

            } else {

                gen_helper_zapnot(vc, va, load_gpr(ctx, rb));

            }

            break;

        case 0x32:

            /* MSKQL */

            gen_msk_l(ctx, vc, va, rb, islit, lit, 0xff);

            break;

        case 0x34:

            /* SRL */

            if (islit) {

                tcg_gen_shri_i64(vc, va, lit & 0x3f);

            } else {

                tmp = tcg_temp_new();

                vb = load_gpr(ctx, rb);

                tcg_gen_andi_i64(tmp, vb, 0x3f);

                tcg_gen_shr_i64(vc, va, tmp);

                tcg_temp_free(tmp);

            }

            break;

        case 0x36:

            /* EXTQL */

            gen_ext_l(ctx, vc, va, rb, islit, lit, 0xff);

            break;

        case 0x39:

            /* SLL */

            if (islit) {

                tcg_gen_shli_i64(vc, va, lit & 0x3f);

            } else {

                tmp = tcg_temp_new();

                vb = load_gpr(ctx, rb);

                tcg_gen_andi_i64(tmp, vb, 0x3f);

                tcg_gen_shl_i64(vc, va, tmp);

                tcg_temp_free(tmp);

            }

            break;

        case 0x3B:

            /* INSQL */

            gen_ins_l(ctx, vc, va, rb, islit, lit, 0xff);

            break;

        case 0x3C:

            /* SRA */

            if (islit) {

                tcg_gen_sari_i64(vc, va, lit & 0x3f);

            } else {

                tmp = tcg_temp_new();

                vb = load_gpr(ctx, rb);

                tcg_gen_andi_i64(tmp, vb, 0x3f);

                tcg_gen_sar_i64(vc, va, tmp);

                tcg_temp_free(tmp);

            }

            break;

        case 0x52:

            /* MSKWH */

            gen_msk_h(ctx, vc, va, rb, islit, lit, 0x03);

            break;

        case 0x57:

            /* INSWH */

            gen_ins_h(ctx, vc, va, rb, islit, lit, 0x03);

            break;

        case 0x5A:

            /* EXTWH */

            gen_ext_h(ctx, vc, va, rb, islit, lit, 0x03);

            break;

        case 0x62:

            /* MSKLH */

            gen_msk_h(ctx, vc, va, rb, islit, lit, 0x0f);

            break;

        case 0x67:

            /* INSLH */

            gen_ins_h(ctx, vc, va, rb, islit, lit, 0x0f);

            break;

        case 0x6A:

            /* EXTLH */

            gen_ext_h(ctx, vc, va, rb, islit, lit, 0x0f);

            break;

        case 0x72:

            /* MSKQH */

            gen_msk_h(ctx, vc, va, rb, islit, lit, 0xff);

            break;

        case 0x77:

            /* INSQH */

            gen_ins_h(ctx, vc, va, rb, islit, lit, 0xff);

            break;

        case 0x7A:

            /* EXTQH */

            gen_ext_h(ctx, vc, va, rb, islit, lit, 0xff);

            break;

        default:

            goto invalid_opc;

        }

        break;

    case 0x13:

        vc = dest_gpr(ctx, rc);

        vb = load_gpr_lit(ctx, rb, lit, islit);

        va = load_gpr(ctx, ra);

        switch (fn7) {

        case 0x00:

            /* MULL */

            tcg_gen_mul_i64(vc, va, vb);

            tcg_gen_ext32s_i64(vc, vc);

            break;

        case 0x20:

            /* MULQ */

            tcg_gen_mul_i64(vc, va, vb);

            break;

        case 0x30:

            /* UMULH */

            tmp = tcg_temp_new();

            tcg_gen_mulu2_i64(tmp, vc, va, vb);

            tcg_temp_free(tmp);

            break;

        case 0x40:

            /* MULL/V */

            gen_helper_mullv(vc, cpu_env, va, vb);

            break;

        case 0x60:

            /* MULQ/V */

            gen_helper_mulqv(vc, cpu_env, va, vb);

            break;

        default:

            goto invalid_opc;

        }

        break;

    case 0x14:

        REQUIRE_TB_FLAG(TB_FLAGS_AMASK_FIX);

        vc = dest_fpr(ctx, rc);

        switch (fpfn) { /* fn11 & 0x3F */

        case 0x04:

            /* ITOFS */

            REQUIRE_REG_31(rb);

            t32 = tcg_temp_new_i32();

            va = load_gpr(ctx, ra);

            tcg_gen_trunc_i64_i32(t32, va);

            gen_helper_memory_to_s(vc, t32);

            tcg_temp_free_i32(t32);

            break;

        case 0x0A:

            /* SQRTF */

            REQUIRE_REG_31(ra);

            vb = load_fpr(ctx, rb);

            gen_helper_sqrtf(vc, cpu_env, vb);

            break;

        case 0x0B:

            /* SQRTS */

            REQUIRE_REG_31(ra);

            gen_sqrts(ctx, rb, rc, fn11);

            break;

        case 0x14:

            /* ITOFF */

            REQUIRE_REG_31(rb);

            t32 = tcg_temp_new_i32();

            va = load_gpr(ctx, ra);

            tcg_gen_trunc_i64_i32(t32, va);

            gen_helper_memory_to_f(vc, t32);

            tcg_temp_free_i32(t32);

            break;

        case 0x24:

            /* ITOFT */

            REQUIRE_REG_31(rb);

            va = load_gpr(ctx, ra);

            tcg_gen_mov_i64(vc, va);

            break;

        case 0x2A:

            /* SQRTG */

            REQUIRE_REG_31(ra);

            vb = load_fpr(ctx, rb);

            gen_helper_sqrtg(vc, cpu_env, vb);

            break;

        case 0x02B:

            /* SQRTT */

            REQUIRE_REG_31(ra);

            gen_sqrtt(ctx, rb, rc, fn11);

            break;

        default:

            goto invalid_opc;

        }

        break;

    case 0x15:

        /* VAX floating point */

        /* XXX: rounding mode and trap are ignored (!) */

        vc = dest_fpr(ctx, rc);

        vb = load_fpr(ctx, rb);

        va = load_fpr(ctx, ra);

        switch (fpfn) { /* fn11 & 0x3F */

        case 0x00:

            /* ADDF */

            gen_helper_addf(vc, cpu_env, va, vb);

            break;

        case 0x01:

            /* SUBF */

            gen_helper_subf(vc, cpu_env, va, vb);

            break;

        case 0x02:

            /* MULF */

            gen_helper_mulf(vc, cpu_env, va, vb);

            break;

        case 0x03:

            /* DIVF */

            gen_helper_divf(vc, cpu_env, va, vb);

            break;

        case 0x1E:

            /* CVTDG -- TODO */

            REQUIRE_REG_31(ra);

            goto invalid_opc;

        case 0x20:

            /* ADDG */

            gen_helper_addg(vc, cpu_env, va, vb);

            break;

        case 0x21:

            /* SUBG */

            gen_helper_subg(vc, cpu_env, va, vb);

            break;

        case 0x22:

            /* MULG */

            gen_helper_mulg(vc, cpu_env, va, vb);

            break;

        case 0x23:

            /* DIVG */

            gen_helper_divg(vc, cpu_env, va, vb);

            break;

        case 0x25:

            /* CMPGEQ */

            gen_helper_cmpgeq(vc, cpu_env, va, vb);

            break;

        case 0x26:

            /* CMPGLT */

            gen_helper_cmpglt(vc, cpu_env, va, vb);

            break;

        case 0x27:

            /* CMPGLE */

            gen_helper_cmpgle(vc, cpu_env, va, vb);

            break;

        case 0x2C:

            /* CVTGF */

            REQUIRE_REG_31(ra);

            gen_helper_cvtgf(vc, cpu_env, vb);

            break;

        case 0x2D:

            /* CVTGD -- TODO */

            REQUIRE_REG_31(ra);

            goto invalid_opc;

        case 0x2F:

            /* CVTGQ */

            REQUIRE_REG_31(ra);

            gen_helper_cvtgq(vc, cpu_env, vb);

            break;

        case 0x3C:

            /* CVTQF */

            REQUIRE_REG_31(ra);

            gen_helper_cvtqf(vc, cpu_env, vb);

            break;

        case 0x3E:

            /* CVTQG */

            REQUIRE_REG_31(ra);

            gen_helper_cvtqg(vc, cpu_env, vb);

            break;

        default:

            goto invalid_opc;

        }

        break;

    case 0x16:

        /* IEEE floating-point */

        switch (fpfn) { /* fn11 & 0x3F */

        case 0x00:

            /* ADDS */

            gen_adds(ctx, ra, rb, rc, fn11);

            break;

        case 0x01:

            /* SUBS */

            gen_subs(ctx, ra, rb, rc, fn11);

            break;

        case 0x02:

            /* MULS */

            gen_muls(ctx, ra, rb, rc, fn11);

            break;

        case 0x03:

            /* DIVS */

            gen_divs(ctx, ra, rb, rc, fn11);

            break;

        case 0x20:

            /* ADDT */

            gen_addt(ctx, ra, rb, rc, fn11);

            break;

        case 0x21:

            /* SUBT */

            gen_subt(ctx, ra, rb, rc, fn11);

            break;

        case 0x22:

            /* MULT */

            gen_mult(ctx, ra, rb, rc, fn11);

            break;

        case 0x23:

            /* DIVT */

            gen_divt(ctx, ra, rb, rc, fn11);

            break;

        case 0x24:

            /* CMPTUN */

            gen_cmptun(ctx, ra, rb, rc, fn11);

            break;

        case 0x25:

            /* CMPTEQ */

            gen_cmpteq(ctx, ra, rb, rc, fn11);

            break;

        case 0x26:

            /* CMPTLT */

            gen_cmptlt(ctx, ra, rb, rc, fn11);

            break;

        case 0x27:

            /* CMPTLE */

            gen_cmptle(ctx, ra, rb, rc, fn11);

            break;

        case 0x2C:

            REQUIRE_REG_31(ra);

            if (fn11 == 0x2AC || fn11 == 0x6AC) {

                /* CVTST */

                gen_cvtst(ctx, rb, rc, fn11);

            } else {

                /* CVTTS */

                gen_cvtts(ctx, rb, rc, fn11);

            }

            break;

        case 0x2F:

            /* CVTTQ */

            REQUIRE_REG_31(ra);

            gen_cvttq(ctx, rb, rc, fn11);

            break;

        case 0x3C:

            /* CVTQS */

            REQUIRE_REG_31(ra);

            gen_cvtqs(ctx, rb, rc, fn11);

            break;

        case 0x3E:

            /* CVTQT */

            REQUIRE_REG_31(ra);

            gen_cvtqt(ctx, rb, rc, fn11);

            break;

        default:

            goto invalid_opc;

        }

        break;

    case 0x17:

        switch (fn11) {

        case 0x010:

            /* CVTLQ */

            REQUIRE_REG_31(ra);

            vc = dest_fpr(ctx, rc);

            vb = load_fpr(ctx, rb);

            gen_cvtlq(vc, vb);

            break;

        case 0x020:

            /* CPYS */

            if (rc == 31) {

                /* Special case CPYS as FNOP.  */

            } else {

                vc = dest_fpr(ctx, rc);

                va = load_fpr(ctx, ra);

                if (ra == rb) {

                    /* Special case CPYS as FMOV.  */

                    tcg_gen_mov_i64(vc, va);

                } else {

                    vb = load_fpr(ctx, rb);

                    gen_cpy_mask(vc, va, vb, 0, 0x8000000000000000ULL);

                }

            }

            break;

        case 0x021:

            /* CPYSN */

            vc = dest_fpr(ctx, rc);

            vb = load_fpr(ctx, rb);

            va = load_fpr(ctx, ra);

            gen_cpy_mask(vc, va, vb, 1, 0x8000000000000000ULL);

            break;

        case 0x022:

            /* CPYSE */

            vc = dest_fpr(ctx, rc);

            vb = load_fpr(ctx, rb);

            va = load_fpr(ctx, ra);

            gen_cpy_mask(vc, va, vb, 0, 0xFFF0000000000000ULL);

            break;

        case 0x024:

            /* MT_FPCR */

            va = load_fpr(ctx, ra);

            gen_helper_store_fpcr(cpu_env, va);

            if (ctx->tb_rm == QUAL_RM_D) {

                /* Re-do the copy of the rounding mode to fp_status

                   the next time we use dynamic rounding.  */

                ctx->tb_rm = -1;

            }

            break;

        case 0x025:

            /* MF_FPCR */

            va = dest_fpr(ctx, ra);

            gen_helper_load_fpcr(va, cpu_env);

            break;

        case 0x02A:

            /* FCMOVEQ */

            gen_fcmov(ctx, TCG_COND_EQ, ra, rb, rc);

            break;

        case 0x02B:

            /* FCMOVNE */

            gen_fcmov(ctx, TCG_COND_NE, ra, rb, rc);

            break;

        case 0x02C:

            /* FCMOVLT */

            gen_fcmov(ctx, TCG_COND_LT, ra, rb, rc);

            break;

        case 0x02D:

            /* FCMOVGE */

            gen_fcmov(ctx, TCG_COND_GE, ra, rb, rc);

            break;

        case 0x02E:

            /* FCMOVLE */

            gen_fcmov(ctx, TCG_COND_LE, ra, rb, rc);

            break;

        case 0x02F:

            /* FCMOVGT */

            gen_fcmov(ctx, TCG_COND_GT, ra, rb, rc);

            break;

        case 0x030:

            /* CVTQL */

            REQUIRE_REG_31(ra);

            vc = dest_fpr(ctx, rc);

            vb = load_fpr(ctx, rb);

            gen_cvtql(vc, vb);

            break;

        case 0x130:

            /* CVTQL/V */

        case 0x530:

            /* CVTQL/SV */

            REQUIRE_REG_31(ra);

            /* ??? I'm pretty sure there's nothing that /sv needs to do that

               /v doesn't do.  The only thing I can think is that /sv is a

               valid instruction merely for completeness in the ISA.  */

            vc = dest_fpr(ctx, rc);

            vb = load_fpr(ctx, rb);

            gen_helper_cvtql_v_input(cpu_env, vb);

            gen_cvtql(vc, vb);

            break;

        default:

            goto invalid_opc;

        }

        break;

    case 0x18:

        switch ((uint16_t)disp16) {

        case 0x0000:

            /* TRAPB */

            /* No-op.  */

            break;

        case 0x0400:

            /* EXCB */

            /* No-op.  */

            break;

        case 0x4000:

            /* MB */

            /* No-op */

            break;

        case 0x4400:

            /* WMB */

            /* No-op */

            break;

        case 0x8000:

            /* FETCH */

            /* No-op */

            break;

        case 0xA000:

            /* FETCH_M */

            /* No-op */

            break;

        case 0xC000:

            /* RPCC */

            va = dest_gpr(ctx, ra);

            if (ctx->tb->cflags & CF_USE_ICOUNT) {

                gen_io_start();

                gen_helper_load_pcc(va, cpu_env);

                gen_io_end();

                ret = EXIT_PC_STALE;

            } else {

                gen_helper_load_pcc(va, cpu_env);

            }

            break;

        case 0xE000:

            /* RC */

            gen_rx(ra, 0);

            break;

        case 0xE800:

            /* ECB */

            break;

        case 0xF000:

            /* RS */

            gen_rx(ra, 1);

            break;

        case 0xF800:

            /* WH64 */

            /* No-op */

            break;

        default:

            goto invalid_opc;

        }

        break;

    case 0x19:

        /* HW_MFPR (PALcode) */

#ifndef CONFIG_USER_ONLY

        REQUIRE_TB_FLAG(TB_FLAGS_PAL_MODE);

        va = dest_gpr(ctx, ra);

        ret = gen_mfpr(ctx, va, insn & 0xffff);

        break;

#else

        goto invalid_opc;

#endif

    case 0x1A:

        /* JMP, JSR, RET, JSR_COROUTINE.  These only differ by the branch

           prediction stack action, which of course we don't implement.  */

        vb = load_gpr(ctx, rb);

        tcg_gen_andi_i64(cpu_pc, vb, ~3);

        if (ra != 31) {

            tcg_gen_movi_i64(cpu_ir[ra], ctx->pc);

        }

        ret = EXIT_PC_UPDATED;

        break;

    case 0x1B:

        /* HW_LD (PALcode) */

#ifndef CONFIG_USER_ONLY

        REQUIRE_TB_FLAG(TB_FLAGS_PAL_MODE);

        {

            TCGv addr = tcg_temp_new();

            vb = load_gpr(ctx, rb);

            va = dest_gpr(ctx, ra);

            tcg_gen_addi_i64(addr, vb, disp12);

            switch ((insn >> 12) & 0xF) {

            case 0x0:

                /* Longword physical access (hw_ldl/p) */

                gen_helper_ldl_phys(va, cpu_env, addr);

                break;

            case 0x1:

                /* Quadword physical access (hw_ldq/p) */

                gen_helper_ldq_phys(va, cpu_env, addr);

                break;

            case 0x2:

                /* Longword physical access with lock (hw_ldl_l/p) */

                gen_helper_ldl_l_phys(va, cpu_env, addr);

                break;

            case 0x3:

                /* Quadword physical access with lock (hw_ldq_l/p) */

                gen_helper_ldq_l_phys(va, cpu_env, addr);

                break;

            case 0x4:

                /* Longword virtual PTE fetch (hw_ldl/v) */

                goto invalid_opc;

            case 0x5:

                /* Quadword virtual PTE fetch (hw_ldq/v) */

                goto invalid_opc;

                break;

            case 0x6:

                /* Incpu_ir[ra]id */

                goto invalid_opc;

            case 0x7:

                /* Incpu_ir[ra]id */

                goto invalid_opc;

            case 0x8:

                /* Longword virtual access (hw_ldl) */

                goto invalid_opc;

            case 0x9:

                /* Quadword virtual access (hw_ldq) */

                goto invalid_opc;

            case 0xA:

                /* Longword virtual access with protection check (hw_ldl/w) */

                tcg_gen_qemu_ld_i64(va, addr, MMU_KERNEL_IDX, MO_LESL);

                break;

            case 0xB:

                /* Quadword virtual access with protection check (hw_ldq/w) */

                tcg_gen_qemu_ld_i64(va, addr, MMU_KERNEL_IDX, MO_LEQ);

                break;

            case 0xC:

                /* Longword virtual access with alt access mode (hw_ldl/a)*/

                goto invalid_opc;

            case 0xD:

                /* Quadword virtual access with alt access mode (hw_ldq/a) */

                goto invalid_opc;

            case 0xE:

                /* Longword virtual access with alternate access mode and

                   protection checks (hw_ldl/wa) */

                tcg_gen_qemu_ld_i64(va, addr, MMU_USER_IDX, MO_LESL);

                break;

            case 0xF:

                /* Quadword virtual access with alternate access mode and

                   protection checks (hw_ldq/wa) */

                tcg_gen_qemu_ld_i64(va, addr, MMU_USER_IDX, MO_LEQ);

                break;

            }

            tcg_temp_free(addr);

            break;

        }

#else

        goto invalid_opc;

#endif

    case 0x1C:

        vc = dest_gpr(ctx, rc);

        if (fn7 == 0x70) {

            /* FTOIT */

            REQUIRE_TB_FLAG(TB_FLAGS_AMASK_FIX);

            REQUIRE_REG_31(rb);

            va = load_fpr(ctx, ra);

            tcg_gen_mov_i64(vc, va);

            break;

        } else if (fn7 == 0x78) {

            /* FTOIS */

            REQUIRE_TB_FLAG(TB_FLAGS_AMASK_FIX);

            REQUIRE_REG_31(rb);

            t32 = tcg_temp_new_i32();

            va = load_fpr(ctx, ra);

            gen_helper_s_to_memory(t32, va);

            tcg_gen_ext_i32_i64(vc, t32);

            tcg_temp_free_i32(t32);

            break;

        }

        vb = load_gpr_lit(ctx, rb, lit, islit);

        switch (fn7) {

        case 0x00:

            /* SEXTB */

            REQUIRE_TB_FLAG(TB_FLAGS_AMASK_BWX);

            REQUIRE_REG_31(ra);

            tcg_gen_ext8s_i64(vc, vb);

            break;

        case 0x01:

            /* SEXTW */

            REQUIRE_TB_FLAG(TB_FLAGS_AMASK_BWX);

            REQUIRE_REG_31(ra);

            tcg_gen_ext16s_i64(vc, vb);

            break;

        case 0x30:

            /* CTPOP */

            REQUIRE_TB_FLAG(TB_FLAGS_AMASK_CIX);

            REQUIRE_REG_31(ra);

            gen_helper_ctpop(vc, vb);

            break;

        case 0x31:

            /* PERR */

            REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI);

            va = load_gpr(ctx, ra);

            gen_helper_perr(vc, va, vb);

            break;

        case 0x32:

            /* CTLZ */

            REQUIRE_TB_FLAG(TB_FLAGS_AMASK_CIX);

            REQUIRE_REG_31(ra);

            gen_helper_ctlz(vc, vb);

            break;

        case 0x33:

            /* CTTZ */

            REQUIRE_TB_FLAG(TB_FLAGS_AMASK_CIX);

            REQUIRE_REG_31(ra);

            gen_helper_cttz(vc, vb);

            break;

        case 0x34:

            /* UNPKBW */

            REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI);

            REQUIRE_REG_31(ra);

            gen_helper_unpkbw(vc, vb);

            break;

        case 0x35:

            /* UNPKBL */

            REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI);

            REQUIRE_REG_31(ra);

            gen_helper_unpkbl(vc, vb);

            break;

        case 0x36:

            /* PKWB */

            REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI);

            REQUIRE_REG_31(ra);

            gen_helper_pkwb(vc, vb);

            break;

        case 0x37:

            /* PKLB */

            REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI);

            REQUIRE_REG_31(ra);

            gen_helper_pklb(vc, vb);

            break;

        case 0x38:

            /* MINSB8 */

            REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI);

            va = load_gpr(ctx, ra);

            gen_helper_minsb8(vc, va, vb);

            break;

        case 0x39:

            /* MINSW4 */

            REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI);

            va = load_gpr(ctx, ra);

            gen_helper_minsw4(vc, va, vb);

            break;

        case 0x3A:

            /* MINUB8 */

            REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI);

            va = load_gpr(ctx, ra);

            gen_helper_minub8(vc, va, vb);

            break;

        case 0x3B:

            /* MINUW4 */

            REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI);

            va = load_gpr(ctx, ra);

            gen_helper_minuw4(vc, va, vb);

            break;

        case 0x3C:

            /* MAXUB8 */

            REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI);

            va = load_gpr(ctx, ra);

            gen_helper_maxub8(vc, va, vb);

            break;

        case 0x3D:

            /* MAXUW4 */

            REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI);

            va = load_gpr(ctx, ra);

            gen_helper_maxuw4(vc, va, vb);

            break;

        case 0x3E:

            /* MAXSB8 */

            REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI);

            va = load_gpr(ctx, ra);

            gen_helper_maxsb8(vc, va, vb);

            break;

        case 0x3F:

            /* MAXSW4 */

            REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI);

            va = load_gpr(ctx, ra);

            gen_helper_maxsw4(vc, va, vb);

            break;

        default:

            goto invalid_opc;

        }

        break;

    case 0x1D:

        /* HW_MTPR (PALcode) */

#ifndef CONFIG_USER_ONLY

        REQUIRE_TB_FLAG(TB_FLAGS_PAL_MODE);

        vb = load_gpr(ctx, rb);

        ret = gen_mtpr(ctx, vb, insn & 0xffff);

        break;

#else

        goto invalid_opc;

#endif

    case 0x1E:

        /* HW_RET (PALcode) */

#ifndef CONFIG_USER_ONLY

        REQUIRE_TB_FLAG(TB_FLAGS_PAL_MODE);

        if (rb == 31) {

            /* Pre-EV6 CPUs interpreted this as HW_REI, loading the return

               address from EXC_ADDR.  This turns out to be useful for our

               emulation PALcode, so continue to accept it.  */

            tmp = tcg_temp_new();

            tcg_gen_ld_i64(tmp, cpu_env, offsetof(CPUAlphaState, exc_addr));

            gen_helper_hw_ret(cpu_env, tmp);

            tcg_temp_free(tmp);

        } else {

            gen_helper_hw_ret(cpu_env, load_gpr(ctx, rb));

        }

        ret = EXIT_PC_UPDATED;

        break;

#else

        goto invalid_opc;

#endif

    case 0x1F:

        /* HW_ST (PALcode) */

#ifndef CONFIG_USER_ONLY

        REQUIRE_TB_FLAG(TB_FLAGS_PAL_MODE);

        {

            TCGv addr = tcg_temp_new();

            va = load_gpr(ctx, ra);

            vb = load_gpr(ctx, rb);

            tcg_gen_addi_i64(addr, vb, disp12);

            switch ((insn >> 12) & 0xF) {

            case 0x0:

                /* Longword physical access */

                gen_helper_stl_phys(cpu_env, addr, va);

                break;

            case 0x1:

                /* Quadword physical access */

                gen_helper_stq_phys(cpu_env, addr, va);

                break;

            case 0x2:

                /* Longword physical access with lock */

                gen_helper_stl_c_phys(dest_gpr(ctx, ra), cpu_env, addr, va);

                break;

            case 0x3:

                /* Quadword physical access with lock */

                gen_helper_stq_c_phys(dest_gpr(ctx, ra), cpu_env, addr, va);

                break;

            case 0x4:

                /* Longword virtual access */

                goto invalid_opc;

            case 0x5:

                /* Quadword virtual access */

                goto invalid_opc;

            case 0x6:

                /* Invalid */

                goto invalid_opc;

            case 0x7:

                /* Invalid */

                goto invalid_opc;

            case 0x8:

                /* Invalid */

                goto invalid_opc;

            case 0x9:

                /* Invalid */

                goto invalid_opc;

            case 0xA:

                /* Invalid */

                goto invalid_opc;

            case 0xB:

                /* Invalid */

                goto invalid_opc;

            case 0xC:

                /* Longword virtual access with alternate access mode */

                goto invalid_opc;

            case 0xD:

                /* Quadword virtual access with alternate access mode */

                goto invalid_opc;

            case 0xE:

                /* Invalid */

                goto invalid_opc;

            case 0xF:

                /* Invalid */

                goto invalid_opc;

            }

            tcg_temp_free(addr);

            break;

        }

#else

        goto invalid_opc;

#endif

    case 0x20:

        /* LDF */

        gen_load_mem(ctx, &gen_qemu_ldf, ra, rb, disp16, 1, 0);

        break;

    case 0x21:

        /* LDG */

        gen_load_mem(ctx, &gen_qemu_ldg, ra, rb, disp16, 1, 0);

        break;

    case 0x22:

        /* LDS */

        gen_load_mem(ctx, &gen_qemu_lds, ra, rb, disp16, 1, 0);

        break;

    case 0x23:

        /* LDT */

        gen_load_mem(ctx, &tcg_gen_qemu_ld64, ra, rb, disp16, 1, 0);

        break;

    case 0x24:

        /* STF */

        gen_store_mem(ctx, &gen_qemu_stf, ra, rb, disp16, 1, 0);

        break;

    case 0x25:

        /* STG */

        gen_store_mem(ctx, &gen_qemu_stg, ra, rb, disp16, 1, 0);

        break;

    case 0x26:

        /* STS */

        gen_store_mem(ctx, &gen_qemu_sts, ra, rb, disp16, 1, 0);

        break;

    case 0x27:

        /* STT */

        gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 1, 0);

        break;

    case 0x28:

        /* LDL */

        gen_load_mem(ctx, &tcg_gen_qemu_ld32s, ra, rb, disp16, 0, 0);

        break;

    case 0x29:

        /* LDQ */

        gen_load_mem(ctx, &tcg_gen_qemu_ld64, ra, rb, disp16, 0, 0);

        break;

    case 0x2A:

        /* LDL_L */

        gen_load_mem(ctx, &gen_qemu_ldl_l, ra, rb, disp16, 0, 0);

        break;

    case 0x2B:

        /* LDQ_L */

        gen_load_mem(ctx, &gen_qemu_ldq_l, ra, rb, disp16, 0, 0);

        break;

    case 0x2C:

        /* STL */

        gen_store_mem(ctx, &tcg_gen_qemu_st32, ra, rb, disp16, 0, 0);

        break;

    case 0x2D:

        /* STQ */

        gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 0, 0);

        break;

    case 0x2E:

        /* STL_C */

        ret = gen_store_conditional(ctx, ra, rb, disp16, 0);

        break;

    case 0x2F:

        /* STQ_C */

        ret = gen_store_conditional(ctx, ra, rb, disp16, 1);

        break;

    case 0x30:

        /* BR */

        ret = gen_bdirect(ctx, ra, disp21);

        break;

    case 0x31: /* FBEQ */

        ret = gen_fbcond(ctx, TCG_COND_EQ, ra, disp21);

        break;

    case 0x32: /* FBLT */

        ret = gen_fbcond(ctx, TCG_COND_LT, ra, disp21);

        break;

    case 0x33: /* FBLE */

        ret = gen_fbcond(ctx, TCG_COND_LE, ra, disp21);

        break;

    case 0x34:

        /* BSR */

        ret = gen_bdirect(ctx, ra, disp21);

        break;

    case 0x35: /* FBNE */

        ret = gen_fbcond(ctx, TCG_COND_NE, ra, disp21);

        break;

    case 0x36: /* FBGE */

        ret = gen_fbcond(ctx, TCG_COND_GE, ra, disp21);

        break;

    case 0x37: /* FBGT */

        ret = gen_fbcond(ctx, TCG_COND_GT, ra, disp21);

        break;

    case 0x38:

        /* BLBC */

        ret = gen_bcond(ctx, TCG_COND_EQ, ra, disp21, 1);

        break;

    case 0x39:

        /* BEQ */

        ret = gen_bcond(ctx, TCG_COND_EQ, ra, disp21, 0);

        break;

    case 0x3A:

        /* BLT */

        ret = gen_bcond(ctx, TCG_COND_LT, ra, disp21, 0);

        break;

    case 0x3B:

        /* BLE */

        ret = gen_bcond(ctx, TCG_COND_LE, ra, disp21, 0);

        break;

    case 0x3C:

        /* BLBS */

        ret = gen_bcond(ctx, TCG_COND_NE, ra, disp21, 1);

        break;

    case 0x3D:

        /* BNE */

        ret = gen_bcond(ctx, TCG_COND_NE, ra, disp21, 0);

        break;

    case 0x3E:

        /* BGE */

        ret = gen_bcond(ctx, TCG_COND_GE, ra, disp21, 0);

        break;

    case 0x3F:

        /* BGT */

        ret = gen_bcond(ctx, TCG_COND_GT, ra, disp21, 0);

        break;

    invalid_opc:

        ret = gen_invalid(ctx);

        break;

    }

    return ret;

}


CPUMIPSState *cpu_mips_init (const char *cpu_model)

{

    CPUMIPSState *env;

    const mips_def_t *def;

    def = cpu_mips_find_by_name(cpu_model);

    if (!def)

        return NULL;

    env = qemu_mallocz(sizeof(CPUMIPSState));

    env->cpu_model = def;

    cpu_exec_init(env);

    env->cpu_model_str = cpu_model;

    mips_tcg_init();

    cpu_reset(env);

    qemu_init_vcpu(env);

    return env;

}


static void *qpa_thread_out (void *arg)

{

    PAVoiceOut *pa = arg;

    HWVoiceOut *hw = &pa->hw;

    int threshold;

    threshold = conf.divisor ? hw->samples / conf.divisor : 0;

    if (audio_pt_lock (&pa->pt, AUDIO_FUNC)) {

        return NULL;

    }

    for (;;) {

        int decr, to_mix, rpos;

        for (;;) {

            if (pa->done) {

                goto exit;

            }

            if (pa->live > threshold) {

                break;

            }

            if (audio_pt_wait (&pa->pt, AUDIO_FUNC)) {

                goto exit;

            }

        }

        decr = to_mix = pa->live;

        rpos = hw->rpos;

        if (audio_pt_unlock (&pa->pt, AUDIO_FUNC)) {

            return NULL;

        }

        while (to_mix) {

            int error;

            int chunk = audio_MIN (to_mix, hw->samples - rpos);

            struct st_sample *src = hw->mix_buf + rpos;

            hw->clip (pa->pcm_buf, src, chunk);

            if (pa_simple_write (pa->s, pa->pcm_buf,

                                 chunk << hw->info.shift, &error) < 0) {

                qpa_logerr (error, "pa_simple_write failed\n");

                return NULL;

            }

            rpos = (rpos + chunk) % hw->samples;

            to_mix -= chunk;

        }

        if (audio_pt_lock (&pa->pt, AUDIO_FUNC)) {

            return NULL;

        }

        pa->rpos = rpos;

        pa->live -= decr;

        pa->decr += decr;

    }

 exit:

    audio_pt_unlock (&pa->pt, AUDIO_FUNC);

    return NULL;

}


static void complete_collecting_data(Flash *s)

{

    int i;

    s->cur_addr = 0;

    for (i = 0; i < get_addr_length(s); ++i) {

        s->cur_addr <<= 8;

        s->cur_addr |= s->data[i];

    }

    if (get_addr_length(s) == 3) {

        s->cur_addr += s->ear * MAX_3BYTES_SIZE;

    }

    s->state = STATE_IDLE;

    switch (s->cmd_in_progress) {

    case DPP:

    case QPP:

    case PP:

    case PP4:

    case PP4_4:

        s->state = STATE_PAGE_PROGRAM;

        break;

    case READ:

    case READ4:

    case FAST_READ:

    case FAST_READ4:

    case DOR:

    case DOR4:

    case QOR:

    case QOR4:

    case DIOR:

    case DIOR4:

    case QIOR:

    case QIOR4:

        s->state = STATE_READ;

        break;

    case ERASE_4K:

    case ERASE4_4K:

    case ERASE_32K:

    case ERASE4_32K:

    case ERASE_SECTOR:

    case ERASE4_SECTOR:

        flash_erase(s, s->cur_addr, s->cmd_in_progress);

        break;

    case WRSR:

        switch (get_man(s)) {

        case MAN_SPANSION:

            s->quad_enable = !!(s->data[1] & 0x02);

            break;

        case MAN_MACRONIX:

            s->quad_enable = extract32(s->data[0], 6, 1);

            if (s->len > 1) {

                s->four_bytes_address_mode = extract32(s->data[1], 5, 1);

            }

            break;

        default:

            break;

        }

        if (s->write_enable) {

            s->write_enable = false;

        }

        break;

    case EXTEND_ADDR_WRITE:

        s->ear = s->data[0];

        break;

    case WNVCR:

        s->nonvolatile_cfg = s->data[0] | (s->data[1] << 8);

        break;

    case WVCR:

        s->volatile_cfg = s->data[0];

        break;

    case WEVCR:

        s->enh_volatile_cfg = s->data[0];

        break;

    default:

        break;

    }

}


static inline void gen_op_fpexception_im(int fsr_flags)

{

    TCGv r_const;

    tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~FSR_FTT_MASK);

    tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags);

    r_const = tcg_const_i32(TT_FP_EXCP);

    tcg_gen_helper_0_1(raise_exception, r_const);

    tcg_temp_free(r_const);

}


static int msf_probe(AVProbeData *p)
{
    if (memcmp(p->buf, "MSF", 3))
        return 0;
    if (AV_RB32(p->buf+8) <= 0)
        return 0;
    if (AV_RB32(p->buf+16) <= 0)
        return 0;
    return AVPROBE_SCORE_MAX / 3 * 2;
}


static void check_exception(PowerPCCPU *cpu, sPAPREnvironment *spapr,

                            uint32_t token, uint32_t nargs,

                            target_ulong args,

                            uint32_t nret, target_ulong rets)

{

    uint32_t mask, buf, len, event_len;

    uint64_t xinfo;

    sPAPREventLogEntry *event;

    struct rtas_error_log *hdr;

    if ((nargs < 6) || (nargs > 7) || nret != 1) {

        rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);

        return;

    }

    xinfo = rtas_ld(args, 1);

    mask = rtas_ld(args, 2);

    buf = rtas_ld(args, 4);

    len = rtas_ld(args, 5);

    if (nargs == 7) {

        xinfo |= (uint64_t)rtas_ld(args, 6) << 32;

    }

    event = rtas_event_log_dequeue(mask);

    if (!event) {

        goto out_no_events;

    }

    hdr = event->data;

    event_len = be32_to_cpu(hdr->extended_length) + sizeof(*hdr);

    if (event_len < len) {

        len = event_len;

    }

    cpu_physical_memory_write(buf, event->data, len);

    rtas_st(rets, 0, RTAS_OUT_SUCCESS);

    g_free(event->data);

    g_free(event);

    /* according to PAPR+, the IRQ must be left asserted, or re-asserted, if

     * there are still pending events to be fetched via check-exception. We

     * do the latter here, since our code relies on edge-triggered

     * interrupts.

     */

    if (rtas_event_log_contains(mask)) {

        qemu_irq_pulse(xics_get_qirq(spapr->icp, spapr->check_exception_irq));

    }

    return;

out_no_events:

    rtas_st(rets, 0, RTAS_OUT_NO_ERRORS_FOUND);

}


static void raw_fd_pool_put(RawAIOCB *acb)

{

    BDRVRawState *s = acb->common.bs->opaque;

    int i;

    for (i = 0; i < RAW_FD_POOL_SIZE; i++) {

        if (s->fd_pool[i] == acb->fd) {

            close(s->fd_pool[i]);

            s->fd_pool[i] = -1;

        }

    }

}


static void test_redirector_rx(void)

{

    int backend_sock[2], send_sock;

    char *cmdline;

    uint32_t ret = 0, len = 0;

    char send_buf[] = "Hello!!";

    char sock_path0[] = "filter-redirector0.XXXXXX";

    char sock_path1[] = "filter-redirector1.XXXXXX";

    char *recv_buf;

    uint32_t size = sizeof(send_buf);

    size = htonl(size);

    ret = socketpair(PF_UNIX, SOCK_STREAM, 0, backend_sock);

    g_assert_cmpint(ret, !=, -1);

    ret = mkstemp(sock_path0);

    g_assert_cmpint(ret, !=, -1);

    ret = mkstemp(sock_path1);

    g_assert_cmpint(ret, !=, -1);

    cmdline = g_strdup_printf("-netdev socket,id=qtest-bn0,fd=%d "

                "-device rtl8139,netdev=qtest-bn0,id=qtest-e0 "

                "-chardev socket,id=redirector0,path=%s,server,nowait "

                "-chardev socket,id=redirector1,path=%s,server,nowait "

                "-chardev socket,id=redirector2,path=%s,nowait "

                "-object filter-redirector,id=qtest-f0,netdev=qtest-bn0,"

                "queue=rx,indev=redirector0 "

                "-object filter-redirector,id=qtest-f1,netdev=qtest-bn0,"

                "queue=rx,outdev=redirector2 "

                "-object filter-redirector,id=qtest-f2,netdev=qtest-bn0,"

                "queue=rx,indev=redirector1 "

                , backend_sock[1], sock_path0, sock_path1, sock_path0);

    qtest_start(cmdline);

    g_free(cmdline);

    struct iovec iov[] = {

        {

            .iov_base = &size,

            .iov_len = sizeof(size),

        }, {

            .iov_base = send_buf,

            .iov_len = sizeof(send_buf),

        },

    };

    send_sock = unix_connect(sock_path1, NULL);

    g_assert_cmpint(send_sock, !=, -1);

    /* send a qmp command to guarantee that 'connected' is setting to true. */

    qmp_discard_response("{ 'execute' : 'query-status'}");

    ret = iov_send(send_sock, iov, 2, 0, sizeof(size) + sizeof(send_buf));

    g_assert_cmpint(ret, ==, sizeof(send_buf) + sizeof(size));

    close(send_sock);

    ret = qemu_recv(backend_sock[0], &len, sizeof(len), 0);

    g_assert_cmpint(ret, ==, sizeof(len));

    len = ntohl(len);

    g_assert_cmpint(len, ==, sizeof(send_buf));

    recv_buf = g_malloc(len);

    ret = qemu_recv(backend_sock[0], recv_buf, len, 0);

    g_assert_cmpstr(recv_buf, ==, send_buf);

    g_free(recv_buf);

    unlink(sock_path0);

    unlink(sock_path1);

    qtest_end();

}


static void cpu_openrisc_load_kernel(ram_addr_t ram_size,

                                     const char *kernel_filename,

                                     OpenRISCCPU *cpu)

{

    long kernel_size;

    uint64_t elf_entry;

    hwaddr entry;

    if (kernel_filename && !qtest_enabled()) {

        kernel_size = load_elf(kernel_filename, NULL, NULL,

                               &elf_entry, NULL, NULL, 1, EM_OPENRISC,

                               1, 0);

        entry = elf_entry;

        if (kernel_size < 0) {

            kernel_size = load_uimage(kernel_filename,

                                      &entry, NULL, NULL, NULL, NULL);

        }

        if (kernel_size < 0) {

            kernel_size = load_image_targphys(kernel_filename,

                                              KERNEL_LOAD_ADDR,

                                              ram_size - KERNEL_LOAD_ADDR);

            entry = KERNEL_LOAD_ADDR;

        }

        if (kernel_size < 0) {

            fprintf(stderr, "QEMU: couldn't load the kernel '%s'\n",

                    kernel_filename);

            exit(1);

        }

        cpu->env.pc = entry;

    }

}


static void configure_rtc_date_offset(const char *startdate, int legacy)

{

    time_t rtc_start_date;

    struct tm tm;

    if (!strcmp(startdate, "now") && legacy) {

        rtc_date_offset = -1;

    } else {

        if (sscanf(startdate, "%d-%d-%dT%d:%d:%d",

                   &tm.tm_year,

                   &tm.tm_mon,

                   &tm.tm_mday,

                   &tm.tm_hour,

                   &tm.tm_min,

                   &tm.tm_sec) == 6) {

            /* OK */

        } else if (sscanf(startdate, "%d-%d-%d",

                          &tm.tm_year,

                          &tm.tm_mon,

                          &tm.tm_mday) == 3) {

            tm.tm_hour = 0;

            tm.tm_min = 0;

            tm.tm_sec = 0;

        } else {

            goto date_fail;

        }

        tm.tm_year -= 1900;

        tm.tm_mon--;

        rtc_start_date = mktimegm(&tm);

        if (rtc_start_date == -1) {

        date_fail:

            fprintf(stderr, "Invalid date format. Valid formats are:\n"

                            "'2006-06-17T16:01:21' or '2006-06-17'\n");

            exit(1);

        }

        rtc_date_offset = time(NULL) - rtc_start_date;

    }

}


void ppc_slb_invalidate_all (CPUPPCState *env)

{

    /* XXX: TODO */

    tlb_flush(env, 1);

}


int load_image_targphys(const char *filename,

			target_phys_addr_t addr, int max_sz)

{

    FILE *f;

    size_t got;

    f = fopen(filename, "rb");

    if (!f) return -1;

    got = fread_targphys(addr, max_sz, f);

    if (ferror(f)) { fclose(f); return -1; }

    fclose(f);

    return got;

}


int gdbserver_start(int port)

{

    gdbserver_fd = gdbserver_open(port);

    if (gdbserver_fd < 0)

        return -1;

    /* accept connections */

    gdb_accept (NULL);

    return 0;

}


CaptureVoiceOut *AUD_add_capture (

    AudioState *s,

    audsettings_t *as,

    struct audio_capture_ops *ops,

    void *cb_opaque

    )

{

    CaptureVoiceOut *cap;

    struct capture_callback *cb;

    if (!s) {

        /* XXX suppress */

        s = &glob_audio_state;

    }

    if (audio_validate_settings (as)) {

        dolog ("Invalid settings were passed when trying to add capture\n");

        audio_print_settings (as);

        goto err0;

    }

    cb = audio_calloc (AUDIO_FUNC, 1, sizeof (*cb));

    if (!cb) {

        dolog ("Could not allocate capture callback information, size %zu\n",

               sizeof (*cb));

        goto err0;

    }

    cb->ops = *ops;

    cb->opaque = cb_opaque;

    cap = audio_pcm_capture_find_specific (s, as);

    if (cap) {

        LIST_INSERT_HEAD (&cap->cb_head, cb, entries);

        return cap;

    }

    else {

        HWVoiceOut *hw;

        CaptureVoiceOut *cap;

        cap = audio_calloc (AUDIO_FUNC, 1, sizeof (*cap));

        if (!cap) {

            dolog ("Could not allocate capture voice, size %zu\n",

                   sizeof (*cap));

            goto err1;

        }

        hw = &cap->hw;

        LIST_INIT (&hw->sw_head);

        LIST_INIT (&cap->cb_head);

        /* XXX find a more elegant way */

        hw->samples = 4096 * 4;

        hw->mix_buf = audio_calloc (AUDIO_FUNC, hw->samples,

                                    sizeof (st_sample_t));

        if (!hw->mix_buf) {

            dolog ("Could not allocate capture mix buffer (%d samples)\n",

                   hw->samples);

            goto err2;

        }

        audio_pcm_init_info (&hw->info, as);

        cap->buf = audio_calloc (AUDIO_FUNC, hw->samples, 1 << hw->info.shift);

        if (!cap->buf) {

            dolog ("Could not allocate capture buffer "

                   "(%d samples, each %d bytes)\n",

                   hw->samples, 1 << hw->info.shift);

            goto err3;

        }

        hw->clip = mixeng_clip

            [hw->info.nchannels == 2]

            [hw->info.sign]

            [hw->info.swap_endianness]

            [audio_bits_to_index (hw->info.bits)];

        LIST_INSERT_HEAD (&s->cap_head, cap, entries);

        LIST_INSERT_HEAD (&cap->cb_head, cb, entries);

        hw = NULL;

        while ((hw = audio_pcm_hw_find_any_out (s, hw))) {

            audio_attach_capture (s, hw);

        }

        return cap;

    err3:

        qemu_free (cap->hw.mix_buf);

    err2:

        qemu_free (cap);

    err1:

        qemu_free (cb);

    err0:

        return NULL;

    }

}


static int nbd_co_writev(BlockDriverState *bs, int64_t sector_num,

                         int nb_sectors, QEMUIOVector *qiov)

{

    BDRVNBDState *s = bs->opaque;

    return nbd_client_session_co_writev(&s->client, sector_num,

                                        nb_sectors, qiov);

}


static void megasas_mmio_write(void *opaque, target_phys_addr_t addr,

                               uint64_t val, unsigned size)

{

    MegasasState *s = opaque;

    uint64_t frame_addr;

    uint32_t frame_count;

    int i;

    trace_megasas_mmio_writel(addr, val);

    switch (addr) {

    case MFI_IDB:

        if (val & MFI_FWINIT_ABORT) {

            /* Abort all pending cmds */

            for (i = 0; i < s->fw_cmds; i++) {

                megasas_abort_command(&s->frames[i]);

            }

        }

        if (val & MFI_FWINIT_READY) {

            /* move to FW READY */

            megasas_soft_reset(s);

        }

        if (val & MFI_FWINIT_MFIMODE) {

            /* discard MFIs */

        }

        break;

    case MFI_OMSK:

        s->intr_mask = val;

        if (!megasas_intr_enabled(s) && !msix_enabled(&s->dev)) {

            trace_megasas_irq_lower();

            qemu_irq_lower(s->dev.irq[0]);

        }

        if (megasas_intr_enabled(s)) {

            trace_megasas_intr_enabled();

        } else {

            trace_megasas_intr_disabled();

        }

        break;

    case MFI_ODCR0:

        s->doorbell = 0;

        if (s->producer_pa && megasas_intr_enabled(s)) {

            /* Update reply queue pointer */

            trace_megasas_qf_update(s->reply_queue_head, s->busy);

            stl_le_phys(s->producer_pa, s->reply_queue_head);

            if (!msix_enabled(&s->dev)) {

                trace_megasas_irq_lower();

                qemu_irq_lower(s->dev.irq[0]);

            }

        }

        break;

    case MFI_IQPH:

        /* Received high 32 bits of a 64 bit MFI frame address */

        s->frame_hi = val;

        break;

    case MFI_IQPL:

        /* Received low 32 bits of a 64 bit MFI frame address */

    case MFI_IQP:

        /* Received 32 bit MFI frame address */

        frame_addr = (val & ~0x1F);

        /* Add possible 64 bit offset */

        frame_addr |= ((uint64_t)s->frame_hi << 32);

        s->frame_hi = 0;

        frame_count = (val >> 1) & 0xF;

        megasas_handle_frame(s, frame_addr, frame_count);

        break;

    default:

        trace_megasas_mmio_invalid_writel(addr, val);

        break;

    }

}


static int mpjpeg_read_packet(AVFormatContext *s, AVPacket *pkt)

{

    int size;

    int ret;

    MPJPEGDemuxContext *mpjpeg = s->priv_data;

    if (mpjpeg->boundary == NULL) {

        mpjpeg->boundary = av_strdup("--");

        mpjpeg->searchstr = av_strdup("\r\n--");

        if (!mpjpeg->boundary || !mpjpeg->searchstr) {

            av_freep(&mpjpeg->boundary);

            av_freep(&mpjpeg->searchstr);

            return AVERROR(ENOMEM);

        }

        mpjpeg->searchstr_len = strlen(mpjpeg->searchstr);

    }

    ret = parse_multipart_header(s->pb, &size, mpjpeg->boundary, s);

    if (ret < 0)

        return ret;

    if (size > 0) {

        /* size has been provided to us in MIME header */

        ret = av_get_packet(s->pb, pkt, size);

    } else {

        /* no size was given -- we read until the next boundary or end-of-file */

        int remaining = 0, len;

        const int read_chunk = 2048;

        av_init_packet(pkt);

        pkt->data = NULL;

        pkt->size = 0;

        pkt->pos  = avio_tell(s->pb);

        /* we may need to return as much as all we've read back to the buffer */

        ffio_ensure_seekback(s->pb, read_chunk);

        while ((ret = av_append_packet(s->pb, pkt, read_chunk - remaining)) >= 0) {

            /* scan the new data */

            len = ret + remaining;

            char *start = pkt->data + pkt->size - len;

            do {

                if (!memcmp(start, mpjpeg->searchstr, mpjpeg->searchstr_len)) {

                    // got the boundary! rewind the stream

                    avio_seek(s->pb, -(len-2), SEEK_CUR);

                    pkt->size -= (len-2);

                    return pkt->size;

                }

                len--;

                start++;

            } while (len >= mpjpeg->searchstr_len);

            remaining = len;

        }

        /* error or EOF occurred */

        if (ret == AVERROR_EOF) {

            ret = pkt->size > 0 ? pkt->size : AVERROR_EOF;

        } else {

            av_packet_unref(pkt);

        }

    }

    return ret;

}


static void gen_flt3_arith (DisasContext *ctx, uint32_t opc,

                            int fd, int fr, int fs, int ft)

{

    const char *opn = "flt3_arith";

    switch (opc) {

    case OPC_ALNV_PS:

        check_cp1_64bitmode(ctx);

        {

            TCGv t0 = tcg_temp_local_new();

            TCGv_i32 fp = tcg_temp_new_i32();

            TCGv_i32 fph = tcg_temp_new_i32();

            int l1 = gen_new_label();

            int l2 = gen_new_label();

            gen_load_gpr(t0, fr);

            tcg_gen_andi_tl(t0, t0, 0x7);

            tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1);

            gen_load_fpr32(fp, fs);

            gen_load_fpr32h(ctx, fph, fs);

            gen_store_fpr32(fp, fd);

            gen_store_fpr32h(ctx, fph, fd);

            tcg_gen_br(l2);

            gen_set_label(l1);

            tcg_gen_brcondi_tl(TCG_COND_NE, t0, 4, l2);

            tcg_temp_free(t0);

#ifdef TARGET_WORDS_BIGENDIAN

            gen_load_fpr32(fp, fs);

            gen_load_fpr32h(ctx, fph, ft);

            gen_store_fpr32h(ctx, fp, fd);

            gen_store_fpr32(fph, fd);

#else

            gen_load_fpr32h(ctx, fph, fs);

            gen_load_fpr32(fp, ft);

            gen_store_fpr32(fph, fd);

            gen_store_fpr32h(ctx, fp, fd);

#endif

            gen_set_label(l2);

            tcg_temp_free_i32(fp);

            tcg_temp_free_i32(fph);

        }

        opn = "alnv.ps";

        break;

    case OPC_MADD_S:

        check_cop1x(ctx);

        {

            TCGv_i32 fp0 = tcg_temp_new_i32();

            TCGv_i32 fp1 = tcg_temp_new_i32();

            TCGv_i32 fp2 = tcg_temp_new_i32();

            gen_load_fpr32(fp0, fs);

            gen_load_fpr32(fp1, ft);

            gen_load_fpr32(fp2, fr);

            gen_helper_float_madd_s(fp2, cpu_env, fp0, fp1, fp2);

            tcg_temp_free_i32(fp0);

            tcg_temp_free_i32(fp1);

            gen_store_fpr32(fp2, fd);

            tcg_temp_free_i32(fp2);

        }

        opn = "madd.s";

        break;

    case OPC_MADD_D:

        check_cop1x(ctx);

        check_cp1_registers(ctx, fd | fs | ft | fr);

        {

            TCGv_i64 fp0 = tcg_temp_new_i64();

            TCGv_i64 fp1 = tcg_temp_new_i64();

            TCGv_i64 fp2 = tcg_temp_new_i64();

            gen_load_fpr64(ctx, fp0, fs);

            gen_load_fpr64(ctx, fp1, ft);

            gen_load_fpr64(ctx, fp2, fr);

            gen_helper_float_madd_d(fp2, cpu_env, fp0, fp1, fp2);

            tcg_temp_free_i64(fp0);

            tcg_temp_free_i64(fp1);

            gen_store_fpr64(ctx, fp2, fd);

            tcg_temp_free_i64(fp2);

        }

        opn = "madd.d";

        break;

    case OPC_MADD_PS:

        check_cp1_64bitmode(ctx);

        {

            TCGv_i64 fp0 = tcg_temp_new_i64();

            TCGv_i64 fp1 = tcg_temp_new_i64();

            TCGv_i64 fp2 = tcg_temp_new_i64();

            gen_load_fpr64(ctx, fp0, fs);

            gen_load_fpr64(ctx, fp1, ft);

            gen_load_fpr64(ctx, fp2, fr);

            gen_helper_float_madd_ps(fp2, cpu_env, fp0, fp1, fp2);

            tcg_temp_free_i64(fp0);

            tcg_temp_free_i64(fp1);

            gen_store_fpr64(ctx, fp2, fd);

            tcg_temp_free_i64(fp2);

        }

        opn = "madd.ps";

        break;

    case OPC_MSUB_S:

        check_cop1x(ctx);

        {

            TCGv_i32 fp0 = tcg_temp_new_i32();

            TCGv_i32 fp1 = tcg_temp_new_i32();

            TCGv_i32 fp2 = tcg_temp_new_i32();

            gen_load_fpr32(fp0, fs);

            gen_load_fpr32(fp1, ft);

            gen_load_fpr32(fp2, fr);

            gen_helper_float_msub_s(fp2, cpu_env, fp0, fp1, fp2);

            tcg_temp_free_i32(fp0);

            tcg_temp_free_i32(fp1);

            gen_store_fpr32(fp2, fd);

            tcg_temp_free_i32(fp2);

        }

        opn = "msub.s";

        break;

    case OPC_MSUB_D:

        check_cop1x(ctx);

        check_cp1_registers(ctx, fd | fs | ft | fr);

        {

            TCGv_i64 fp0 = tcg_temp_new_i64();

            TCGv_i64 fp1 = tcg_temp_new_i64();

            TCGv_i64 fp2 = tcg_temp_new_i64();

            gen_load_fpr64(ctx, fp0, fs);

            gen_load_fpr64(ctx, fp1, ft);

            gen_load_fpr64(ctx, fp2, fr);

            gen_helper_float_msub_d(fp2, cpu_env, fp0, fp1, fp2);

            tcg_temp_free_i64(fp0);

            tcg_temp_free_i64(fp1);

            gen_store_fpr64(ctx, fp2, fd);

            tcg_temp_free_i64(fp2);

        }

        opn = "msub.d";

        break;

    case OPC_MSUB_PS:

        check_cp1_64bitmode(ctx);

        {

            TCGv_i64 fp0 = tcg_temp_new_i64();

            TCGv_i64 fp1 = tcg_temp_new_i64();

            TCGv_i64 fp2 = tcg_temp_new_i64();

            gen_load_fpr64(ctx, fp0, fs);

            gen_load_fpr64(ctx, fp1, ft);

            gen_load_fpr64(ctx, fp2, fr);

            gen_helper_float_msub_ps(fp2, cpu_env, fp0, fp1, fp2);

            tcg_temp_free_i64(fp0);

            tcg_temp_free_i64(fp1);

            gen_store_fpr64(ctx, fp2, fd);

            tcg_temp_free_i64(fp2);

        }

        opn = "msub.ps";

        break;

    case OPC_NMADD_S:

        check_cop1x(ctx);

        {

            TCGv_i32 fp0 = tcg_temp_new_i32();

            TCGv_i32 fp1 = tcg_temp_new_i32();

            TCGv_i32 fp2 = tcg_temp_new_i32();

            gen_load_fpr32(fp0, fs);

            gen_load_fpr32(fp1, ft);

            gen_load_fpr32(fp2, fr);

            gen_helper_float_nmadd_s(fp2, cpu_env, fp0, fp1, fp2);

            tcg_temp_free_i32(fp0);

            tcg_temp_free_i32(fp1);

            gen_store_fpr32(fp2, fd);

            tcg_temp_free_i32(fp2);

        }

        opn = "nmadd.s";

        break;

    case OPC_NMADD_D:

        check_cop1x(ctx);

        check_cp1_registers(ctx, fd | fs | ft | fr);

        {

            TCGv_i64 fp0 = tcg_temp_new_i64();

            TCGv_i64 fp1 = tcg_temp_new_i64();

            TCGv_i64 fp2 = tcg_temp_new_i64();

            gen_load_fpr64(ctx, fp0, fs);

            gen_load_fpr64(ctx, fp1, ft);

            gen_load_fpr64(ctx, fp2, fr);

            gen_helper_float_nmadd_d(fp2, cpu_env, fp0, fp1, fp2);

            tcg_temp_free_i64(fp0);

            tcg_temp_free_i64(fp1);

            gen_store_fpr64(ctx, fp2, fd);

            tcg_temp_free_i64(fp2);

        }

        opn = "nmadd.d";

        break;

    case OPC_NMADD_PS:

        check_cp1_64bitmode(ctx);

        {

            TCGv_i64 fp0 = tcg_temp_new_i64();

            TCGv_i64 fp1 = tcg_temp_new_i64();

            TCGv_i64 fp2 = tcg_temp_new_i64();

            gen_load_fpr64(ctx, fp0, fs);

            gen_load_fpr64(ctx, fp1, ft);

            gen_load_fpr64(ctx, fp2, fr);

            gen_helper_float_nmadd_ps(fp2, cpu_env, fp0, fp1, fp2);

            tcg_temp_free_i64(fp0);

            tcg_temp_free_i64(fp1);

            gen_store_fpr64(ctx, fp2, fd);

            tcg_temp_free_i64(fp2);

        }

        opn = "nmadd.ps";

        break;

    case OPC_NMSUB_S:

        check_cop1x(ctx);

        {

            TCGv_i32 fp0 = tcg_temp_new_i32();

            TCGv_i32 fp1 = tcg_temp_new_i32();

            TCGv_i32 fp2 = tcg_temp_new_i32();

            gen_load_fpr32(fp0, fs);

            gen_load_fpr32(fp1, ft);

            gen_load_fpr32(fp2, fr);

            gen_helper_float_nmsub_s(fp2, cpu_env, fp0, fp1, fp2);

            tcg_temp_free_i32(fp0);

            tcg_temp_free_i32(fp1);

            gen_store_fpr32(fp2, fd);

            tcg_temp_free_i32(fp2);

        }

        opn = "nmsub.s";

        break;

    case OPC_NMSUB_D:

        check_cop1x(ctx);

        check_cp1_registers(ctx, fd | fs | ft | fr);

        {

            TCGv_i64 fp0 = tcg_temp_new_i64();

            TCGv_i64 fp1 = tcg_temp_new_i64();

            TCGv_i64 fp2 = tcg_temp_new_i64();

            gen_load_fpr64(ctx, fp0, fs);

            gen_load_fpr64(ctx, fp1, ft);

            gen_load_fpr64(ctx, fp2, fr);

            gen_helper_float_nmsub_d(fp2, cpu_env, fp0, fp1, fp2);

            tcg_temp_free_i64(fp0);

            tcg_temp_free_i64(fp1);

            gen_store_fpr64(ctx, fp2, fd);

            tcg_temp_free_i64(fp2);

        }

        opn = "nmsub.d";

        break;

    case OPC_NMSUB_PS:

        check_cp1_64bitmode(ctx);

        {

            TCGv_i64 fp0 = tcg_temp_new_i64();

            TCGv_i64 fp1 = tcg_temp_new_i64();

            TCGv_i64 fp2 = tcg_temp_new_i64();

            gen_load_fpr64(ctx, fp0, fs);

            gen_load_fpr64(ctx, fp1, ft);

            gen_load_fpr64(ctx, fp2, fr);

            gen_helper_float_nmsub_ps(fp2, cpu_env, fp0, fp1, fp2);

            tcg_temp_free_i64(fp0);

            tcg_temp_free_i64(fp1);

            gen_store_fpr64(ctx, fp2, fd);

            tcg_temp_free_i64(fp2);

        }

        opn = "nmsub.ps";

        break;

    default:

        MIPS_INVAL(opn);

        generate_exception (ctx, EXCP_RI);

        return;

    }

    (void)opn; /* avoid a compiler warning */

    MIPS_DEBUG("%s %s, %s, %s, %s", opn, fregnames[fd], fregnames[fr],

               fregnames[fs], fregnames[ft]);

}


static void pc_compat_2_1(MachineState *machine)

{

    PCMachineState *pcms = PC_MACHINE(machine);

    pc_compat_2_2(machine);

    pcms->enforce_aligned_dimm = false;

    smbios_uuid_encoded = false;

    x86_cpu_change_kvm_default("svm", NULL);

}


qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus,

                        qemu_irq **irqs, qemu_irq irq_out)

{

    openpic_t *opp;

    int i, m;

    struct {

        const char             *name;

        MemoryRegionOps const  *ops;

        hwaddr      start_addr;

        ram_addr_t              size;

    } const list[] = {

        {"glb", &openpic_glb_ops, OPENPIC_GLB_REG_START, OPENPIC_GLB_REG_SIZE},

        {"tmr", &openpic_tmr_ops, OPENPIC_TMR_REG_START, OPENPIC_TMR_REG_SIZE},

        {"src", &openpic_src_ops, OPENPIC_SRC_REG_START, OPENPIC_SRC_REG_SIZE},

        {"cpu", &openpic_cpu_ops, OPENPIC_CPU_REG_START, OPENPIC_CPU_REG_SIZE},

    };

    /* XXX: for now, only one CPU is supported */

    if (nb_cpus != 1)

        return NULL;

    opp = g_malloc0(sizeof(openpic_t));

    memory_region_init(&opp->mem, "openpic", 0x40000);

    for (i = 0; i < ARRAY_SIZE(list); i++) {

        memory_region_init_io(&opp->sub_io_mem[i], list[i].ops, opp,

                              list[i].name, list[i].size);

        memory_region_add_subregion(&opp->mem, list[i].start_addr,

                                    &opp->sub_io_mem[i]);

    }

    //    isu_base &= 0xFFFC0000;

    opp->nb_cpus = nb_cpus;

    opp->max_irq = OPENPIC_MAX_IRQ;

    opp->irq_ipi0 = OPENPIC_IRQ_IPI0;

    opp->irq_tim0 = OPENPIC_IRQ_TIM0;

    /* Set IRQ types */

    for (i = 0; i < OPENPIC_EXT_IRQ; i++) {

        opp->src[i].type = IRQ_EXTERNAL;

    }

    for (; i < OPENPIC_IRQ_TIM0; i++) {

        opp->src[i].type = IRQ_SPECIAL;

    }

    m = OPENPIC_IRQ_IPI0;

    for (; i < m; i++) {

        opp->src[i].type = IRQ_TIMER;

    }

    for (; i < OPENPIC_MAX_IRQ; i++) {

        opp->src[i].type = IRQ_INTERNAL;

    }

    for (i = 0; i < nb_cpus; i++)

        opp->dst[i].irqs = irqs[i];

    opp->irq_out = irq_out;

    register_savevm(&opp->pci_dev.qdev, "openpic", 0, 2,

                    openpic_save, openpic_load, opp);

    qemu_register_reset(openpic_reset, opp);

    opp->irq_raise = openpic_irq_raise;

    opp->reset = openpic_reset;

    if (pmem)

        *pmem = &opp->mem;

    return qemu_allocate_irqs(openpic_set_irq, opp, opp->max_irq);

}


void do_interrupt(CPUARMState *env)

{

    uint32_t addr;

    uint32_t mask;

    int new_mode;

    uint32_t offset;

    if (IS_M(env)) {

        do_interrupt_v7m(env);

        return;

    }

    /* TODO: Vectored interrupt controller.  */

    switch (env->exception_index) {

    case EXCP_UDEF:

        new_mode = ARM_CPU_MODE_UND;

        addr = 0x04;

        mask = CPSR_I;

        if (env->thumb)

            offset = 2;

        else

            offset = 4;

        break;

    case EXCP_SWI:

        if (semihosting_enabled) {

            /* Check for semihosting interrupt.  */

            if (env->thumb) {

                mask = lduw_code(env->regs[15] - 2) & 0xff;

            } else {

                mask = ldl_code(env->regs[15] - 4) & 0xffffff;

            }

            /* Only intercept calls from privileged modes, to provide some

               semblance of security.  */

            if (((mask == 0x123456 && !env->thumb)

                    || (mask == 0xab && env->thumb))

                  && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {

                env->regs[0] = do_arm_semihosting(env);

                return;

            }

        }

        new_mode = ARM_CPU_MODE_SVC;

        addr = 0x08;

        mask = CPSR_I;

        /* The PC already points to the next instruction.  */

        offset = 0;

        break;

    case EXCP_BKPT:

        /* See if this is a semihosting syscall.  */

        if (env->thumb && semihosting_enabled) {

            mask = lduw_code(env->regs[15]) & 0xff;

            if (mask == 0xab

                  && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {

                env->regs[15] += 2;

                env->regs[0] = do_arm_semihosting(env);

                return;

            }

        }

        /* Fall through to prefetch abort.  */

    case EXCP_PREFETCH_ABORT:

        new_mode = ARM_CPU_MODE_ABT;

        addr = 0x0c;

        mask = CPSR_A | CPSR_I;

        offset = 4;

        break;

    case EXCP_DATA_ABORT:

        new_mode = ARM_CPU_MODE_ABT;

        addr = 0x10;

        mask = CPSR_A | CPSR_I;

        offset = 8;

        break;

    case EXCP_IRQ:

        new_mode = ARM_CPU_MODE_IRQ;

        addr = 0x18;

        /* Disable IRQ and imprecise data aborts.  */

        mask = CPSR_A | CPSR_I;

        offset = 4;

        break;

    case EXCP_FIQ:

        new_mode = ARM_CPU_MODE_FIQ;

        addr = 0x1c;

        /* Disable FIQ, IRQ and imprecise data aborts.  */

        mask = CPSR_A | CPSR_I | CPSR_F;

        offset = 4;

        break;

    default:

        cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);

        return; /* Never happens.  Keep compiler happy.  */

    }

    /* High vectors.  */

    if (env->cp15.c1_sys & (1 << 13)) {

        addr += 0xffff0000;

    }

    switch_mode (env, new_mode);

    env->spsr = cpsr_read(env);

    /* Clear IT bits.  */

    env->condexec_bits = 0;

    /* Switch to the new mode, and to the correct instruction set.  */

    env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;

    env->uncached_cpsr |= mask;

    env->thumb = (env->cp15.c1_sys & (1 << 30)) != 0;

    env->regs[14] = env->regs[15] + offset;

    env->regs[15] = addr;

    env->interrupt_request |= CPU_INTERRUPT_EXITTB;

}


int stpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba, uint8_t ar)

{

    CPUS390XState *env = &cpu->env;

    uint32_t fh;

    ZpciFib fib;

    S390PCIBusDevice *pbdev;

    uint32_t data;

    uint64_t cc = ZPCI_PCI_LS_OK;

    if (env->psw.mask & PSW_MASK_PSTATE) {

        program_interrupt(env, PGM_PRIVILEGED, 6);

        return 0;

    }

    fh = env->regs[r1] >> 32;

    if (fiba & 0x7) {

        program_interrupt(env, PGM_SPECIFICATION, 6);

        return 0;

    }

    pbdev = s390_pci_find_dev_by_fh(fh);

    if (!pbdev) {

        setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);

        return 0;

    }

    memset(&fib, 0, sizeof(fib));

    stq_p(&fib.pba, pbdev->pba);

    stq_p(&fib.pal, pbdev->pal);

    stq_p(&fib.iota, pbdev->g_iota);

    stq_p(&fib.aibv, pbdev->routes.adapter.ind_addr);

    stq_p(&fib.aisb, pbdev->routes.adapter.summary_addr);

    stq_p(&fib.fmb_addr, pbdev->fmb_addr);

    data = ((uint32_t)pbdev->isc << 28) | ((uint32_t)pbdev->noi << 16) |

           ((uint32_t)pbdev->routes.adapter.ind_offset << 8) |

           ((uint32_t)pbdev->sum << 7) | pbdev->routes.adapter.summary_offset;

    stl_p(&fib.data, data);

    if (pbdev->fh & FH_MASK_ENABLE) {

        fib.fc |= 0x80;

    }

    if (pbdev->error_state) {

        fib.fc |= 0x40;

    }

    if (pbdev->lgstg_blocked) {

        fib.fc |= 0x20;

    }

    if (pbdev->g_iota) {

        fib.fc |= 0x10;

    }

    if (s390_cpu_virt_mem_write(cpu, fiba, ar, (uint8_t *)&fib, sizeof(fib))) {

        return 0;

    }

    setcc(cpu, cc);

    return 0;

}


static void mv88w8618_wlan_write(void *opaque, target_phys_addr_t offset,

                                 uint64_t value, unsigned size)

{

}


START_TEST(qint_from_int_test)

{

    QInt *qi;

    const int value = -42;

    qi = qint_from_int(value);

    fail_unless(qi != NULL);

    fail_unless(qi->value == value);

    fail_unless(qi->base.refcnt == 1);

    fail_unless(qobject_type(QOBJECT(qi)) == QTYPE_QINT);

    // destroy doesn't exit yet

    g_free(qi);

}


static int kvm_s390_store_adtl_status(S390CPU *cpu, hwaddr addr)

{

    void *mem;

    hwaddr len = ADTL_SAVE_AREA_SIZE;

    mem = cpu_physical_memory_map(addr, &len, 1);

    if (!mem) {

        return -EFAULT;

    }

    if (len != ADTL_SAVE_AREA_SIZE) {

        cpu_physical_memory_unmap(mem, len, 1, 0);

        return -EFAULT;

    }

    memcpy(mem, &cpu->env.vregs, 512);

    cpu_physical_memory_unmap(mem, len, 1, len);

    return 0;

}


int page_unprotect(target_ulong address, unsigned long pc, void *puc)

{

    unsigned int page_index, prot, pindex;

    PageDesc *p, *p1;

    target_ulong host_start, host_end, addr;

    /* Technically this isn't safe inside a signal handler.  However we

       know this only ever happens in a synchronous SEGV handler, so in

       practice it seems to be ok.  */

    mmap_lock();

    host_start = address & qemu_host_page_mask;

    page_index = host_start >> TARGET_PAGE_BITS;

    p1 = page_find(page_index);

    if (!p1) {

        mmap_unlock();

        return 0;

    }

    host_end = host_start + qemu_host_page_size;

    p = p1;

    prot = 0;

    for(addr = host_start;addr < host_end; addr += TARGET_PAGE_SIZE) {

        prot |= p->flags;

        p++;

    }

    /* if the page was really writable, then we change its

       protection back to writable */

    if (prot & PAGE_WRITE_ORG) {

        pindex = (address - host_start) >> TARGET_PAGE_BITS;

        if (!(p1[pindex].flags & PAGE_WRITE)) {

            mprotect((void *)g2h(host_start), qemu_host_page_size,

                     (prot & PAGE_BITS) | PAGE_WRITE);

            p1[pindex].flags |= PAGE_WRITE;

            /* and since the content will be modified, we must invalidate

               the corresponding translated code. */

            tb_invalidate_phys_page(address, pc, puc);

#ifdef DEBUG_TB_CHECK

            tb_invalidate_check(address);

#endif

            mmap_unlock();

            return 1;

        }

    }

    mmap_unlock();

    return 0;

}


static int mov_read_enda(MOVContext *c, ByteIOContext *pb, MOVAtom atom)

{

    AVStream *st = c->fc->streams[c->fc->nb_streams-1];

    int little_endian = get_be16(pb);

    dprintf(c->fc, "enda %d\n", little_endian);

    if (little_endian == 1) {

        switch (st->codec->codec_id) {

        case CODEC_ID_PCM_S24BE:

            st->codec->codec_id = CODEC_ID_PCM_S24LE;

            break;

        case CODEC_ID_PCM_S32BE:

            st->codec->codec_id = CODEC_ID_PCM_S32LE;

            break;

        case CODEC_ID_PCM_F32BE:

            st->codec->codec_id = CODEC_ID_PCM_F32LE;

            break;

        case CODEC_ID_PCM_F64BE:

            st->codec->codec_id = CODEC_ID_PCM_F64LE;

            break;

        default:

            break;

        }

    }

    return 0;

}


static inline int decode_scalar(GetBitContext *gb, int k, int limit, int readsamplesize){

    int x = get_unary_0_9(gb);

    if (x > 8) { /* RICE THRESHOLD */

        /* use alternative encoding */

        x = get_bits(gb, readsamplesize);

    } else {

        if (k >= limit)

            k = limit;

        if (k != 1) {

            int extrabits = show_bits(gb, k);

            /* multiply x by 2^k - 1, as part of their strange algorithm */

            x = (x << k) - x;

            if (extrabits > 1) {

                x += extrabits - 1;

                skip_bits(gb, k);

            } else

                skip_bits(gb, k - 1);

        }

    }

    return x;

}


static void opt_b_frames(const char *arg)

{

    b_frames = atoi(arg);

    if (b_frames > FF_MAX_B_FRAMES) {

        fprintf(stderr, "\nCannot have more than %d B frames, increase FF_MAX_B_FRAMES.\n", FF_MAX_B_FRAMES);

        exit(1);

    } else if (b_frames < 1) {

        fprintf(stderr, "\nNumber of B frames must be higher than 0\n");

        exit(1);

    }

}