/*******************************************************************************
* File Name: cyfitter.h
* 
* PSoC Creator  4.1 Update 1
*
* Description:
* 
* This file is automatically generated by PSoC Creator.
*
********************************************************************************
* Copyright (c) 2007-2017 Cypress Semiconductor.  All rights reserved.
* You may use this file only in accordance with the license, terms, conditions, 
* disclaimers, and limitations in the end user license agreement accompanying 
* the software package with which this file was provided.
********************************************************************************/

#ifndef INCLUDED_CYFITTER_H
#define INCLUDED_CYFITTER_H
#include "cydevice.h"
#include "cydevice_trm.h"

/* ADC */
#define ADC_bSAR_SEQ_ChannelCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB08_09_ACTL
#define ADC_bSAR_SEQ_ChannelCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB08_09_CTL
#define ADC_bSAR_SEQ_ChannelCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB08_09_CTL
#define ADC_bSAR_SEQ_ChannelCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB08_09_CTL
#define ADC_bSAR_SEQ_ChannelCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB08_09_CTL
#define ADC_bSAR_SEQ_ChannelCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB08_09_MSK
#define ADC_bSAR_SEQ_ChannelCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB08_09_MSK
#define ADC_bSAR_SEQ_ChannelCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB08_09_MSK
#define ADC_bSAR_SEQ_ChannelCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB08_09_MSK
#define ADC_bSAR_SEQ_ChannelCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB08_ACTL
#define ADC_bSAR_SEQ_ChannelCounter__CONTROL_REG CYREG_B1_UDB08_CTL
#define ADC_bSAR_SEQ_ChannelCounter__CONTROL_ST_REG CYREG_B1_UDB08_ST_CTL
#define ADC_bSAR_SEQ_ChannelCounter__COUNT_REG CYREG_B1_UDB08_CTL
#define ADC_bSAR_SEQ_ChannelCounter__COUNT_ST_REG CYREG_B1_UDB08_ST_CTL
#define ADC_bSAR_SEQ_ChannelCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB08_MSK_ACTL
#define ADC_bSAR_SEQ_ChannelCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB08_MSK_ACTL
#define ADC_bSAR_SEQ_ChannelCounter__PERIOD_REG CYREG_B1_UDB08_MSK
#define ADC_bSAR_SEQ_ChannelCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB08_09_ACTL
#define ADC_bSAR_SEQ_ChannelCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB08_09_ST
#define ADC_bSAR_SEQ_ChannelCounter_ST__MASK_REG CYREG_B1_UDB08_MSK
#define ADC_bSAR_SEQ_ChannelCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB08_MSK_ACTL
#define ADC_bSAR_SEQ_ChannelCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB08_MSK_ACTL
#define ADC_bSAR_SEQ_ChannelCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB08_ACTL
#define ADC_bSAR_SEQ_ChannelCounter_ST__STATUS_CNT_REG CYREG_B1_UDB08_ST_CTL
#define ADC_bSAR_SEQ_ChannelCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB08_ST_CTL
#define ADC_bSAR_SEQ_ChannelCounter_ST__STATUS_REG CYREG_B1_UDB08_ST
#define ADC_bSAR_SEQ_CtrlReg__0__MASK 0x01u
#define ADC_bSAR_SEQ_CtrlReg__0__POS 0
#define ADC_bSAR_SEQ_CtrlReg__1__MASK 0x02u
#define ADC_bSAR_SEQ_CtrlReg__1__POS 1
#define ADC_bSAR_SEQ_CtrlReg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
#define ADC_bSAR_SEQ_CtrlReg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL
#define ADC_bSAR_SEQ_CtrlReg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL
#define ADC_bSAR_SEQ_CtrlReg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL
#define ADC_bSAR_SEQ_CtrlReg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL
#define ADC_bSAR_SEQ_CtrlReg__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK
#define ADC_bSAR_SEQ_CtrlReg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK
#define ADC_bSAR_SEQ_CtrlReg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK
#define ADC_bSAR_SEQ_CtrlReg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK
#define ADC_bSAR_SEQ_CtrlReg__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL
#define ADC_bSAR_SEQ_CtrlReg__CONTROL_REG CYREG_B0_UDB11_CTL
#define ADC_bSAR_SEQ_CtrlReg__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL
#define ADC_bSAR_SEQ_CtrlReg__COUNT_REG CYREG_B0_UDB11_CTL
#define ADC_bSAR_SEQ_CtrlReg__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL
#define ADC_bSAR_SEQ_CtrlReg__MASK 0x03u
#define ADC_bSAR_SEQ_CtrlReg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
#define ADC_bSAR_SEQ_CtrlReg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
#define ADC_bSAR_SEQ_CtrlReg__PERIOD_REG CYREG_B0_UDB11_MSK
#define ADC_bSAR_SEQ_EOCSts__0__MASK 0x01u
#define ADC_bSAR_SEQ_EOCSts__0__POS 0
#define ADC_bSAR_SEQ_EOCSts__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB09_10_ACTL
#define ADC_bSAR_SEQ_EOCSts__16BIT_STATUS_REG CYREG_B0_UDB09_10_ST
#define ADC_bSAR_SEQ_EOCSts__MASK 0x01u
#define ADC_bSAR_SEQ_EOCSts__MASK_REG CYREG_B0_UDB09_MSK
#define ADC_bSAR_SEQ_EOCSts__STATUS_AUX_CTL_REG CYREG_B0_UDB09_ACTL
#define ADC_bSAR_SEQ_EOCSts__STATUS_REG CYREG_B0_UDB09_ST
#define ADC_FinalBuf__DRQ_CTL CYREG_IDMUX_DRQ_CTL0
#define ADC_FinalBuf__DRQ_NUMBER 0u
#define ADC_FinalBuf__NUMBEROF_TDS 0u
#define ADC_FinalBuf__PRIORITY 2u
#define ADC_FinalBuf__TERMIN_EN 0u
#define ADC_FinalBuf__TERMIN_SEL 0u
#define ADC_FinalBuf__TERMOUT0_EN 1u
#define ADC_FinalBuf__TERMOUT0_SEL 0u
#define ADC_FinalBuf__TERMOUT1_EN 0u
#define ADC_FinalBuf__TERMOUT1_SEL 0u
#define ADC_IntClock__CFG0 CYREG_CLKDIST_DCFG0_CFG0
#define ADC_IntClock__CFG1 CYREG_CLKDIST_DCFG0_CFG1
#define ADC_IntClock__CFG2 CYREG_CLKDIST_DCFG0_CFG2
#define ADC_IntClock__CFG2_SRC_SEL_MASK 0x07u
#define ADC_IntClock__INDEX 0x00u
#define ADC_IntClock__PM_ACT_CFG CYREG_PM_ACT_CFG2
#define ADC_IntClock__PM_ACT_MSK 0x01u
#define ADC_IntClock__PM_STBY_CFG CYREG_PM_STBY_CFG2
#define ADC_IntClock__PM_STBY_MSK 0x01u
#define ADC_IRQ__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define ADC_IRQ__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
#define ADC_IRQ__INTC_MASK 0x01u
#define ADC_IRQ__INTC_NUMBER 0u
#define ADC_IRQ__INTC_PRIOR_NUM 7u
#define ADC_IRQ__INTC_PRIOR_REG CYREG_NVIC_PRI_0
#define ADC_IRQ__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define ADC_IRQ__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
#define ADC_SAR_ADC_SAR__CLK CYREG_SAR0_CLK
#define ADC_SAR_ADC_SAR__CSR0 CYREG_SAR0_CSR0
#define ADC_SAR_ADC_SAR__CSR1 CYREG_SAR0_CSR1
#define ADC_SAR_ADC_SAR__CSR2 CYREG_SAR0_CSR2
#define ADC_SAR_ADC_SAR__CSR3 CYREG_SAR0_CSR3
#define ADC_SAR_ADC_SAR__CSR4 CYREG_SAR0_CSR4
#define ADC_SAR_ADC_SAR__CSR5 CYREG_SAR0_CSR5
#define ADC_SAR_ADC_SAR__CSR6 CYREG_SAR0_CSR6
#define ADC_SAR_ADC_SAR__PM_ACT_CFG CYREG_PM_ACT_CFG11
#define ADC_SAR_ADC_SAR__PM_ACT_MSK 0x01u
#define ADC_SAR_ADC_SAR__PM_STBY_CFG CYREG_PM_STBY_CFG11
#define ADC_SAR_ADC_SAR__PM_STBY_MSK 0x01u
#define ADC_SAR_ADC_SAR__SW0 CYREG_SAR0_SW0
#define ADC_SAR_ADC_SAR__SW2 CYREG_SAR0_SW2
#define ADC_SAR_ADC_SAR__SW3 CYREG_SAR0_SW3
#define ADC_SAR_ADC_SAR__SW4 CYREG_SAR0_SW4
#define ADC_SAR_ADC_SAR__SW6 CYREG_SAR0_SW6
#define ADC_SAR_ADC_SAR__TR0 CYREG_SAR0_TR0
#define ADC_SAR_ADC_SAR__WRK0 CYREG_SAR0_WRK0
#define ADC_SAR_ADC_SAR__WRK1 CYREG_SAR0_WRK1
#define ADC_TempBuf__DRQ_CTL CYREG_IDMUX_DRQ_CTL0
#define ADC_TempBuf__DRQ_NUMBER 1u
#define ADC_TempBuf__NUMBEROF_TDS 0u
#define ADC_TempBuf__PRIORITY 2u
#define ADC_TempBuf__TERMIN_EN 0u
#define ADC_TempBuf__TERMIN_SEL 0u
#define ADC_TempBuf__TERMOUT0_EN 1u
#define ADC_TempBuf__TERMOUT0_SEL 1u
#define ADC_TempBuf__TERMOUT1_EN 0u
#define ADC_TempBuf__TERMOUT1_SEL 0u

/* Analog_Dial */
#define Analog_Dial__0__INTTYPE CYREG_PICU0_INTTYPE7
#define Analog_Dial__0__MASK 0x80u
#define Analog_Dial__0__PC CYREG_PRT0_PC7
#define Analog_Dial__0__PORT 0u
#define Analog_Dial__0__SHIFT 7u
#define Analog_Dial__AG CYREG_PRT0_AG
#define Analog_Dial__AMUX CYREG_PRT0_AMUX
#define Analog_Dial__BIE CYREG_PRT0_BIE
#define Analog_Dial__BIT_MASK CYREG_PRT0_BIT_MASK
#define Analog_Dial__BYP CYREG_PRT0_BYP
#define Analog_Dial__CTL CYREG_PRT0_CTL
#define Analog_Dial__DM0 CYREG_PRT0_DM0
#define Analog_Dial__DM1 CYREG_PRT0_DM1
#define Analog_Dial__DM2 CYREG_PRT0_DM2
#define Analog_Dial__DR CYREG_PRT0_DR
#define Analog_Dial__INP_DIS CYREG_PRT0_INP_DIS
#define Analog_Dial__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU0_BASE
#define Analog_Dial__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
#define Analog_Dial__LCD_EN CYREG_PRT0_LCD_EN
#define Analog_Dial__MASK 0x80u
#define Analog_Dial__PORT 0u
#define Analog_Dial__PRT CYREG_PRT0_PRT
#define Analog_Dial__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
#define Analog_Dial__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
#define Analog_Dial__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
#define Analog_Dial__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
#define Analog_Dial__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
#define Analog_Dial__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
#define Analog_Dial__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
#define Analog_Dial__PS CYREG_PRT0_PS
#define Analog_Dial__SHIFT 7u
#define Analog_Dial__SLW CYREG_PRT0_SLW

/* Analog_RX */
#define Analog_RX__0__INTTYPE CYREG_PICU0_INTTYPE3
#define Analog_RX__0__MASK 0x08u
#define Analog_RX__0__PC CYREG_PRT0_PC3
#define Analog_RX__0__PORT 0u
#define Analog_RX__0__SHIFT 3u
#define Analog_RX__AG CYREG_PRT0_AG
#define Analog_RX__AMUX CYREG_PRT0_AMUX
#define Analog_RX__BIE CYREG_PRT0_BIE
#define Analog_RX__BIT_MASK CYREG_PRT0_BIT_MASK
#define Analog_RX__BYP CYREG_PRT0_BYP
#define Analog_RX__CTL CYREG_PRT0_CTL
#define Analog_RX__DM0 CYREG_PRT0_DM0
#define Analog_RX__DM1 CYREG_PRT0_DM1
#define Analog_RX__DM2 CYREG_PRT0_DM2
#define Analog_RX__DR CYREG_PRT0_DR
#define Analog_RX__INP_DIS CYREG_PRT0_INP_DIS
#define Analog_RX__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU0_BASE
#define Analog_RX__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
#define Analog_RX__LCD_EN CYREG_PRT0_LCD_EN
#define Analog_RX__MASK 0x08u
#define Analog_RX__PORT 0u
#define Analog_RX__PRT CYREG_PRT0_PRT
#define Analog_RX__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
#define Analog_RX__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
#define Analog_RX__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
#define Analog_RX__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
#define Analog_RX__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
#define Analog_RX__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
#define Analog_RX__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
#define Analog_RX__PS CYREG_PRT0_PS
#define Analog_RX__SHIFT 3u
#define Analog_RX__SLW CYREG_PRT0_SLW

/* Analog_RY */
#define Analog_RY__0__INTTYPE CYREG_PICU0_INTTYPE4
#define Analog_RY__0__MASK 0x10u
#define Analog_RY__0__PC CYREG_PRT0_PC4
#define Analog_RY__0__PORT 0u
#define Analog_RY__0__SHIFT 4u
#define Analog_RY__AG CYREG_PRT0_AG
#define Analog_RY__AMUX CYREG_PRT0_AMUX
#define Analog_RY__BIE CYREG_PRT0_BIE
#define Analog_RY__BIT_MASK CYREG_PRT0_BIT_MASK
#define Analog_RY__BYP CYREG_PRT0_BYP
#define Analog_RY__CTL CYREG_PRT0_CTL
#define Analog_RY__DM0 CYREG_PRT0_DM0
#define Analog_RY__DM1 CYREG_PRT0_DM1
#define Analog_RY__DM2 CYREG_PRT0_DM2
#define Analog_RY__DR CYREG_PRT0_DR
#define Analog_RY__INP_DIS CYREG_PRT0_INP_DIS
#define Analog_RY__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU0_BASE
#define Analog_RY__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
#define Analog_RY__LCD_EN CYREG_PRT0_LCD_EN
#define Analog_RY__MASK 0x10u
#define Analog_RY__PORT 0u
#define Analog_RY__PRT CYREG_PRT0_PRT
#define Analog_RY__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
#define Analog_RY__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
#define Analog_RY__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
#define Analog_RY__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
#define Analog_RY__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
#define Analog_RY__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
#define Analog_RY__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
#define Analog_RY__PS CYREG_PRT0_PS
#define Analog_RY__SHIFT 4u
#define Analog_RY__SLW CYREG_PRT0_SLW

/* Analog_RZ */
#define Analog_RZ__0__INTTYPE CYREG_PICU0_INTTYPE5
#define Analog_RZ__0__MASK 0x20u
#define Analog_RZ__0__PC CYREG_PRT0_PC5
#define Analog_RZ__0__PORT 0u
#define Analog_RZ__0__SHIFT 5u
#define Analog_RZ__AG CYREG_PRT0_AG
#define Analog_RZ__AMUX CYREG_PRT0_AMUX
#define Analog_RZ__BIE CYREG_PRT0_BIE
#define Analog_RZ__BIT_MASK CYREG_PRT0_BIT_MASK
#define Analog_RZ__BYP CYREG_PRT0_BYP
#define Analog_RZ__CTL CYREG_PRT0_CTL
#define Analog_RZ__DM0 CYREG_PRT0_DM0
#define Analog_RZ__DM1 CYREG_PRT0_DM1
#define Analog_RZ__DM2 CYREG_PRT0_DM2
#define Analog_RZ__DR CYREG_PRT0_DR
#define Analog_RZ__INP_DIS CYREG_PRT0_INP_DIS
#define Analog_RZ__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU0_BASE
#define Analog_RZ__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
#define Analog_RZ__LCD_EN CYREG_PRT0_LCD_EN
#define Analog_RZ__MASK 0x20u
#define Analog_RZ__PORT 0u
#define Analog_RZ__PRT CYREG_PRT0_PRT
#define Analog_RZ__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
#define Analog_RZ__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
#define Analog_RZ__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
#define Analog_RZ__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
#define Analog_RZ__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
#define Analog_RZ__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
#define Analog_RZ__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
#define Analog_RZ__PS CYREG_PRT0_PS
#define Analog_RZ__SHIFT 5u
#define Analog_RZ__SLW CYREG_PRT0_SLW

/* Analog_Slider */
#define Analog_Slider__0__INTTYPE CYREG_PICU0_INTTYPE6
#define Analog_Slider__0__MASK 0x40u
#define Analog_Slider__0__PC CYREG_PRT0_PC6
#define Analog_Slider__0__PORT 0u
#define Analog_Slider__0__SHIFT 6u
#define Analog_Slider__AG CYREG_PRT0_AG
#define Analog_Slider__AMUX CYREG_PRT0_AMUX
#define Analog_Slider__BIE CYREG_PRT0_BIE
#define Analog_Slider__BIT_MASK CYREG_PRT0_BIT_MASK
#define Analog_Slider__BYP CYREG_PRT0_BYP
#define Analog_Slider__CTL CYREG_PRT0_CTL
#define Analog_Slider__DM0 CYREG_PRT0_DM0
#define Analog_Slider__DM1 CYREG_PRT0_DM1
#define Analog_Slider__DM2 CYREG_PRT0_DM2
#define Analog_Slider__DR CYREG_PRT0_DR
#define Analog_Slider__INP_DIS CYREG_PRT0_INP_DIS
#define Analog_Slider__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU0_BASE
#define Analog_Slider__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
#define Analog_Slider__LCD_EN CYREG_PRT0_LCD_EN
#define Analog_Slider__MASK 0x40u
#define Analog_Slider__PORT 0u
#define Analog_Slider__PRT CYREG_PRT0_PRT
#define Analog_Slider__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
#define Analog_Slider__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
#define Analog_Slider__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
#define Analog_Slider__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
#define Analog_Slider__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
#define Analog_Slider__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
#define Analog_Slider__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
#define Analog_Slider__PS CYREG_PRT0_PS
#define Analog_Slider__SHIFT 6u
#define Analog_Slider__SLW CYREG_PRT0_SLW

/* Analog_X */
#define Analog_X__0__INTTYPE CYREG_PICU0_INTTYPE0
#define Analog_X__0__MASK 0x01u
#define Analog_X__0__PC CYREG_PRT0_PC0
#define Analog_X__0__PORT 0u
#define Analog_X__0__SHIFT 0u
#define Analog_X__AG CYREG_PRT0_AG
#define Analog_X__AMUX CYREG_PRT0_AMUX
#define Analog_X__BIE CYREG_PRT0_BIE
#define Analog_X__BIT_MASK CYREG_PRT0_BIT_MASK
#define Analog_X__BYP CYREG_PRT0_BYP
#define Analog_X__CTL CYREG_PRT0_CTL
#define Analog_X__DM0 CYREG_PRT0_DM0
#define Analog_X__DM1 CYREG_PRT0_DM1
#define Analog_X__DM2 CYREG_PRT0_DM2
#define Analog_X__DR CYREG_PRT0_DR
#define Analog_X__INP_DIS CYREG_PRT0_INP_DIS
#define Analog_X__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU0_BASE
#define Analog_X__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
#define Analog_X__LCD_EN CYREG_PRT0_LCD_EN
#define Analog_X__MASK 0x01u
#define Analog_X__PORT 0u
#define Analog_X__PRT CYREG_PRT0_PRT
#define Analog_X__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
#define Analog_X__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
#define Analog_X__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
#define Analog_X__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
#define Analog_X__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
#define Analog_X__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
#define Analog_X__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
#define Analog_X__PS CYREG_PRT0_PS
#define Analog_X__SHIFT 0u
#define Analog_X__SLW CYREG_PRT0_SLW

/* Analog_Y */
#define Analog_Y__0__INTTYPE CYREG_PICU0_INTTYPE1
#define Analog_Y__0__MASK 0x02u
#define Analog_Y__0__PC CYREG_PRT0_PC1
#define Analog_Y__0__PORT 0u
#define Analog_Y__0__SHIFT 1u
#define Analog_Y__AG CYREG_PRT0_AG
#define Analog_Y__AMUX CYREG_PRT0_AMUX
#define Analog_Y__BIE CYREG_PRT0_BIE
#define Analog_Y__BIT_MASK CYREG_PRT0_BIT_MASK
#define Analog_Y__BYP CYREG_PRT0_BYP
#define Analog_Y__CTL CYREG_PRT0_CTL
#define Analog_Y__DM0 CYREG_PRT0_DM0
#define Analog_Y__DM1 CYREG_PRT0_DM1
#define Analog_Y__DM2 CYREG_PRT0_DM2
#define Analog_Y__DR CYREG_PRT0_DR
#define Analog_Y__INP_DIS CYREG_PRT0_INP_DIS
#define Analog_Y__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU0_BASE
#define Analog_Y__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
#define Analog_Y__LCD_EN CYREG_PRT0_LCD_EN
#define Analog_Y__MASK 0x02u
#define Analog_Y__PORT 0u
#define Analog_Y__PRT CYREG_PRT0_PRT
#define Analog_Y__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
#define Analog_Y__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
#define Analog_Y__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
#define Analog_Y__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
#define Analog_Y__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
#define Analog_Y__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
#define Analog_Y__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
#define Analog_Y__PS CYREG_PRT0_PS
#define Analog_Y__SHIFT 1u
#define Analog_Y__SLW CYREG_PRT0_SLW

/* Analog_Z */
#define Analog_Z__0__INTTYPE CYREG_PICU0_INTTYPE2
#define Analog_Z__0__MASK 0x04u
#define Analog_Z__0__PC CYREG_PRT0_PC2
#define Analog_Z__0__PORT 0u
#define Analog_Z__0__SHIFT 2u
#define Analog_Z__AG CYREG_PRT0_AG
#define Analog_Z__AMUX CYREG_PRT0_AMUX
#define Analog_Z__BIE CYREG_PRT0_BIE
#define Analog_Z__BIT_MASK CYREG_PRT0_BIT_MASK
#define Analog_Z__BYP CYREG_PRT0_BYP
#define Analog_Z__CTL CYREG_PRT0_CTL
#define Analog_Z__DM0 CYREG_PRT0_DM0
#define Analog_Z__DM1 CYREG_PRT0_DM1
#define Analog_Z__DM2 CYREG_PRT0_DM2
#define Analog_Z__DR CYREG_PRT0_DR
#define Analog_Z__INP_DIS CYREG_PRT0_INP_DIS
#define Analog_Z__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU0_BASE
#define Analog_Z__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
#define Analog_Z__LCD_EN CYREG_PRT0_LCD_EN
#define Analog_Z__MASK 0x04u
#define Analog_Z__PORT 0u
#define Analog_Z__PRT CYREG_PRT0_PRT
#define Analog_Z__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
#define Analog_Z__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
#define Analog_Z__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
#define Analog_Z__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
#define Analog_Z__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
#define Analog_Z__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
#define Analog_Z__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
#define Analog_Z__PS CYREG_PRT0_PS
#define Analog_Z__SHIFT 2u
#define Analog_Z__SLW CYREG_PRT0_SLW

/* ButtonReg1 */
#define ButtonReg1_sts_sts_reg__0__MASK 0x01u
#define ButtonReg1_sts_sts_reg__0__POS 0
#define ButtonReg1_sts_sts_reg__1__MASK 0x02u
#define ButtonReg1_sts_sts_reg__1__POS 1
#define ButtonReg1_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL
#define ButtonReg1_sts_sts_reg__16BIT_STATUS_REG CYREG_B1_UDB05_06_ST
#define ButtonReg1_sts_sts_reg__2__MASK 0x04u
#define ButtonReg1_sts_sts_reg__2__POS 2
#define ButtonReg1_sts_sts_reg__3__MASK 0x08u
#define ButtonReg1_sts_sts_reg__3__POS 3
#define ButtonReg1_sts_sts_reg__4__MASK 0x10u
#define ButtonReg1_sts_sts_reg__4__POS 4
#define ButtonReg1_sts_sts_reg__5__MASK 0x20u
#define ButtonReg1_sts_sts_reg__5__POS 5
#define ButtonReg1_sts_sts_reg__6__MASK 0x40u
#define ButtonReg1_sts_sts_reg__6__POS 6
#define ButtonReg1_sts_sts_reg__7__MASK 0x80u
#define ButtonReg1_sts_sts_reg__7__POS 7
#define ButtonReg1_sts_sts_reg__MASK 0xFFu
#define ButtonReg1_sts_sts_reg__MASK_REG CYREG_B1_UDB05_MSK
#define ButtonReg1_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B1_UDB05_ACTL
#define ButtonReg1_sts_sts_reg__STATUS_REG CYREG_B1_UDB05_ST

/* ButtonReg2 */
#define ButtonReg2_sts_sts_reg__0__MASK 0x01u
#define ButtonReg2_sts_sts_reg__0__POS 0
#define ButtonReg2_sts_sts_reg__1__MASK 0x02u
#define ButtonReg2_sts_sts_reg__1__POS 1
#define ButtonReg2_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL
#define ButtonReg2_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB10_11_ST
#define ButtonReg2_sts_sts_reg__2__MASK 0x04u
#define ButtonReg2_sts_sts_reg__2__POS 2
#define ButtonReg2_sts_sts_reg__3__MASK 0x08u
#define ButtonReg2_sts_sts_reg__3__POS 3
#define ButtonReg2_sts_sts_reg__4__MASK 0x10u
#define ButtonReg2_sts_sts_reg__4__POS 4
#define ButtonReg2_sts_sts_reg__5__MASK 0x20u
#define ButtonReg2_sts_sts_reg__5__POS 5
#define ButtonReg2_sts_sts_reg__6__MASK 0x40u
#define ButtonReg2_sts_sts_reg__6__POS 6
#define ButtonReg2_sts_sts_reg__7__MASK 0x80u
#define ButtonReg2_sts_sts_reg__7__POS 7
#define ButtonReg2_sts_sts_reg__MASK 0xFFu
#define ButtonReg2_sts_sts_reg__MASK_REG CYREG_B0_UDB10_MSK
#define ButtonReg2_sts_sts_reg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL
#define ButtonReg2_sts_sts_reg__PER_ST_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL
#define ButtonReg2_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB10_ACTL
#define ButtonReg2_sts_sts_reg__STATUS_CNT_REG CYREG_B0_UDB10_ST_CTL
#define ButtonReg2_sts_sts_reg__STATUS_CONTROL_REG CYREG_B0_UDB10_ST_CTL
#define ButtonReg2_sts_sts_reg__STATUS_REG CYREG_B0_UDB10_ST

/* ButtonReg3 */
#define ButtonReg3_sts_sts_reg__0__MASK 0x01u
#define ButtonReg3_sts_sts_reg__0__POS 0
#define ButtonReg3_sts_sts_reg__1__MASK 0x02u
#define ButtonReg3_sts_sts_reg__1__POS 1
#define ButtonReg3_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB09_10_ACTL
#define ButtonReg3_sts_sts_reg__16BIT_STATUS_REG CYREG_B1_UDB09_10_ST
#define ButtonReg3_sts_sts_reg__2__MASK 0x04u
#define ButtonReg3_sts_sts_reg__2__POS 2
#define ButtonReg3_sts_sts_reg__3__MASK 0x08u
#define ButtonReg3_sts_sts_reg__3__POS 3
#define ButtonReg3_sts_sts_reg__4__MASK 0x10u
#define ButtonReg3_sts_sts_reg__4__POS 4
#define ButtonReg3_sts_sts_reg__5__MASK 0x20u
#define ButtonReg3_sts_sts_reg__5__POS 5
#define ButtonReg3_sts_sts_reg__MASK 0x3Fu
#define ButtonReg3_sts_sts_reg__MASK_REG CYREG_B1_UDB09_MSK
#define ButtonReg3_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B1_UDB09_ACTL
#define ButtonReg3_sts_sts_reg__STATUS_REG CYREG_B1_UDB09_ST

/* Button_17_22 */
#define Button_17_22__0__INTTYPE CYREG_PICU1_INTTYPE2
#define Button_17_22__0__MASK 0x04u
#define Button_17_22__0__PC CYREG_PRT1_PC2
#define Button_17_22__0__PORT 1u
#define Button_17_22__0__SHIFT 2u
#define Button_17_22__1__INTTYPE CYREG_PICU1_INTTYPE3
#define Button_17_22__1__MASK 0x08u
#define Button_17_22__1__PC CYREG_PRT1_PC3
#define Button_17_22__1__PORT 1u
#define Button_17_22__1__SHIFT 3u
#define Button_17_22__2__INTTYPE CYREG_PICU1_INTTYPE4
#define Button_17_22__2__MASK 0x10u
#define Button_17_22__2__PC CYREG_PRT1_PC4
#define Button_17_22__2__PORT 1u
#define Button_17_22__2__SHIFT 4u
#define Button_17_22__3__INTTYPE CYREG_PICU1_INTTYPE5
#define Button_17_22__3__MASK 0x20u
#define Button_17_22__3__PC CYREG_PRT1_PC5
#define Button_17_22__3__PORT 1u
#define Button_17_22__3__SHIFT 5u
#define Button_17_22__4__INTTYPE CYREG_PICU1_INTTYPE6
#define Button_17_22__4__MASK 0x40u
#define Button_17_22__4__PC CYREG_PRT1_PC6
#define Button_17_22__4__PORT 1u
#define Button_17_22__4__SHIFT 6u
#define Button_17_22__5__INTTYPE CYREG_PICU1_INTTYPE7
#define Button_17_22__5__MASK 0x80u
#define Button_17_22__5__PC CYREG_PRT1_PC7
#define Button_17_22__5__PORT 1u
#define Button_17_22__5__SHIFT 7u
#define Button_17_22__AG CYREG_PRT1_AG
#define Button_17_22__AMUX CYREG_PRT1_AMUX
#define Button_17_22__BIE CYREG_PRT1_BIE
#define Button_17_22__BIT_MASK CYREG_PRT1_BIT_MASK
#define Button_17_22__BYP CYREG_PRT1_BYP
#define Button_17_22__CTL CYREG_PRT1_CTL
#define Button_17_22__DM0 CYREG_PRT1_DM0
#define Button_17_22__DM1 CYREG_PRT1_DM1
#define Button_17_22__DM2 CYREG_PRT1_DM2
#define Button_17_22__DR CYREG_PRT1_DR
#define Button_17_22__INP_DIS CYREG_PRT1_INP_DIS
#define Button_17_22__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU1_BASE
#define Button_17_22__LCD_COM_SEG CYREG_PRT1_LCD_COM_SEG
#define Button_17_22__LCD_EN CYREG_PRT1_LCD_EN
#define Button_17_22__MASK 0xFCu
#define Button_17_22__PORT 1u
#define Button_17_22__PRT CYREG_PRT1_PRT
#define Button_17_22__PRTDSI__CAPS_SEL CYREG_PRT1_CAPS_SEL
#define Button_17_22__PRTDSI__DBL_SYNC_IN CYREG_PRT1_DBL_SYNC_IN
#define Button_17_22__PRTDSI__OE_SEL0 CYREG_PRT1_OE_SEL0
#define Button_17_22__PRTDSI__OE_SEL1 CYREG_PRT1_OE_SEL1
#define Button_17_22__PRTDSI__OUT_SEL0 CYREG_PRT1_OUT_SEL0
#define Button_17_22__PRTDSI__OUT_SEL1 CYREG_PRT1_OUT_SEL1
#define Button_17_22__PRTDSI__SYNC_OUT CYREG_PRT1_SYNC_OUT
#define Button_17_22__PS CYREG_PRT1_PS
#define Button_17_22__SHIFT 2u
#define Button_17_22__SLW CYREG_PRT1_SLW

/* Button_1_8 */
#define Button_1_8__0__INTTYPE CYREG_PICU3_INTTYPE0
#define Button_1_8__0__MASK 0x01u
#define Button_1_8__0__PC CYREG_PRT3_PC0
#define Button_1_8__0__PORT 3u
#define Button_1_8__0__SHIFT 0u
#define Button_1_8__1__INTTYPE CYREG_PICU3_INTTYPE1
#define Button_1_8__1__MASK 0x02u
#define Button_1_8__1__PC CYREG_PRT3_PC1
#define Button_1_8__1__PORT 3u
#define Button_1_8__1__SHIFT 1u
#define Button_1_8__2__INTTYPE CYREG_PICU3_INTTYPE2
#define Button_1_8__2__MASK 0x04u
#define Button_1_8__2__PC CYREG_PRT3_PC2
#define Button_1_8__2__PORT 3u
#define Button_1_8__2__SHIFT 2u
#define Button_1_8__3__INTTYPE CYREG_PICU3_INTTYPE3
#define Button_1_8__3__MASK 0x08u
#define Button_1_8__3__PC CYREG_PRT3_PC3
#define Button_1_8__3__PORT 3u
#define Button_1_8__3__SHIFT 3u
#define Button_1_8__4__INTTYPE CYREG_PICU3_INTTYPE4
#define Button_1_8__4__MASK 0x10u
#define Button_1_8__4__PC CYREG_PRT3_PC4
#define Button_1_8__4__PORT 3u
#define Button_1_8__4__SHIFT 4u
#define Button_1_8__5__INTTYPE CYREG_PICU3_INTTYPE5
#define Button_1_8__5__MASK 0x20u
#define Button_1_8__5__PC CYREG_PRT3_PC5
#define Button_1_8__5__PORT 3u
#define Button_1_8__5__SHIFT 5u
#define Button_1_8__6__INTTYPE CYREG_PICU3_INTTYPE6
#define Button_1_8__6__MASK 0x40u
#define Button_1_8__6__PC CYREG_PRT3_PC6
#define Button_1_8__6__PORT 3u
#define Button_1_8__6__SHIFT 6u
#define Button_1_8__7__INTTYPE CYREG_PICU3_INTTYPE7
#define Button_1_8__7__MASK 0x80u
#define Button_1_8__7__PC CYREG_PRT3_PC7
#define Button_1_8__7__PORT 3u
#define Button_1_8__7__SHIFT 7u
#define Button_1_8__AG CYREG_PRT3_AG
#define Button_1_8__AMUX CYREG_PRT3_AMUX
#define Button_1_8__BIE CYREG_PRT3_BIE
#define Button_1_8__BIT_MASK CYREG_PRT3_BIT_MASK
#define Button_1_8__BYP CYREG_PRT3_BYP
#define Button_1_8__CTL CYREG_PRT3_CTL
#define Button_1_8__DM0 CYREG_PRT3_DM0
#define Button_1_8__DM1 CYREG_PRT3_DM1
#define Button_1_8__DM2 CYREG_PRT3_DM2
#define Button_1_8__DR CYREG_PRT3_DR
#define Button_1_8__INP_DIS CYREG_PRT3_INP_DIS
#define Button_1_8__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE
#define Button_1_8__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
#define Button_1_8__LCD_EN CYREG_PRT3_LCD_EN
#define Button_1_8__MASK 0xFFu
#define Button_1_8__PORT 3u
#define Button_1_8__PRT CYREG_PRT3_PRT
#define Button_1_8__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
#define Button_1_8__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
#define Button_1_8__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
#define Button_1_8__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
#define Button_1_8__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
#define Button_1_8__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
#define Button_1_8__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
#define Button_1_8__PS CYREG_PRT3_PS
#define Button_1_8__SHIFT 0u
#define Button_1_8__SLW CYREG_PRT3_SLW

/* Button_9_16 */
#define Button_9_16__0__INTTYPE CYREG_PICU2_INTTYPE0
#define Button_9_16__0__MASK 0x01u
#define Button_9_16__0__PC CYREG_PRT2_PC0
#define Button_9_16__0__PORT 2u
#define Button_9_16__0__SHIFT 0u
#define Button_9_16__1__INTTYPE CYREG_PICU2_INTTYPE1
#define Button_9_16__1__MASK 0x02u
#define Button_9_16__1__PC CYREG_PRT2_PC1
#define Button_9_16__1__PORT 2u
#define Button_9_16__1__SHIFT 1u
#define Button_9_16__2__INTTYPE CYREG_PICU2_INTTYPE2
#define Button_9_16__2__MASK 0x04u
#define Button_9_16__2__PC CYREG_PRT2_PC2
#define Button_9_16__2__PORT 2u
#define Button_9_16__2__SHIFT 2u
#define Button_9_16__3__INTTYPE CYREG_PICU2_INTTYPE3
#define Button_9_16__3__MASK 0x08u
#define Button_9_16__3__PC CYREG_PRT2_PC3
#define Button_9_16__3__PORT 2u
#define Button_9_16__3__SHIFT 3u
#define Button_9_16__4__INTTYPE CYREG_PICU2_INTTYPE4
#define Button_9_16__4__MASK 0x10u
#define Button_9_16__4__PC CYREG_PRT2_PC4
#define Button_9_16__4__PORT 2u
#define Button_9_16__4__SHIFT 4u
#define Button_9_16__5__INTTYPE CYREG_PICU2_INTTYPE5
#define Button_9_16__5__MASK 0x20u
#define Button_9_16__5__PC CYREG_PRT2_PC5
#define Button_9_16__5__PORT 2u
#define Button_9_16__5__SHIFT 5u
#define Button_9_16__6__INTTYPE CYREG_PICU2_INTTYPE6
#define Button_9_16__6__MASK 0x40u
#define Button_9_16__6__PC CYREG_PRT2_PC6
#define Button_9_16__6__PORT 2u
#define Button_9_16__6__SHIFT 6u
#define Button_9_16__7__INTTYPE CYREG_PICU2_INTTYPE7
#define Button_9_16__7__MASK 0x80u
#define Button_9_16__7__PC CYREG_PRT2_PC7
#define Button_9_16__7__PORT 2u
#define Button_9_16__7__SHIFT 7u
#define Button_9_16__AG CYREG_PRT2_AG
#define Button_9_16__AMUX CYREG_PRT2_AMUX
#define Button_9_16__BIE CYREG_PRT2_BIE
#define Button_9_16__BIT_MASK CYREG_PRT2_BIT_MASK
#define Button_9_16__BYP CYREG_PRT2_BYP
#define Button_9_16__CTL CYREG_PRT2_CTL
#define Button_9_16__DM0 CYREG_PRT2_DM0
#define Button_9_16__DM1 CYREG_PRT2_DM1
#define Button_9_16__DM2 CYREG_PRT2_DM2
#define Button_9_16__DR CYREG_PRT2_DR
#define Button_9_16__INP_DIS CYREG_PRT2_INP_DIS
#define Button_9_16__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU2_BASE
#define Button_9_16__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
#define Button_9_16__LCD_EN CYREG_PRT2_LCD_EN
#define Button_9_16__MASK 0xFFu
#define Button_9_16__PORT 2u
#define Button_9_16__PRT CYREG_PRT2_PRT
#define Button_9_16__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
#define Button_9_16__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
#define Button_9_16__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
#define Button_9_16__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
#define Button_9_16__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
#define Button_9_16__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
#define Button_9_16__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
#define Button_9_16__PS CYREG_PRT2_PS
#define Button_9_16__SHIFT 0u
#define Button_9_16__SLW CYREG_PRT2_SLW

/* Clock_1 */
#define Clock_1__CFG0 CYREG_CLKDIST_DCFG2_CFG0
#define Clock_1__CFG1 CYREG_CLKDIST_DCFG2_CFG1
#define Clock_1__CFG2 CYREG_CLKDIST_DCFG2_CFG2
#define Clock_1__CFG2_SRC_SEL_MASK 0x07u
#define Clock_1__INDEX 0x02u
#define Clock_1__PM_ACT_CFG CYREG_PM_ACT_CFG2
#define Clock_1__PM_ACT_MSK 0x04u
#define Clock_1__PM_STBY_CFG CYREG_PM_STBY_CFG2
#define Clock_1__PM_STBY_MSK 0x04u

/* DEBUG_UART_BUART */
#define DEBUG_UART_BUART_sRX_RxBitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB10_11_ACTL
#define DEBUG_UART_BUART_sRX_RxBitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB10_11_CTL
#define DEBUG_UART_BUART_sRX_RxBitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB10_11_CTL
#define DEBUG_UART_BUART_sRX_RxBitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB10_11_CTL
#define DEBUG_UART_BUART_sRX_RxBitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB10_11_CTL
#define DEBUG_UART_BUART_sRX_RxBitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB10_11_MSK
#define DEBUG_UART_BUART_sRX_RxBitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB10_11_MSK
#define DEBUG_UART_BUART_sRX_RxBitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB10_11_MSK
#define DEBUG_UART_BUART_sRX_RxBitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB10_11_MSK
#define DEBUG_UART_BUART_sRX_RxBitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB10_ACTL
#define DEBUG_UART_BUART_sRX_RxBitCounter__CONTROL_REG CYREG_B1_UDB10_CTL
#define DEBUG_UART_BUART_sRX_RxBitCounter__CONTROL_ST_REG CYREG_B1_UDB10_ST_CTL
#define DEBUG_UART_BUART_sRX_RxBitCounter__COUNT_REG CYREG_B1_UDB10_CTL
#define DEBUG_UART_BUART_sRX_RxBitCounter__COUNT_ST_REG CYREG_B1_UDB10_ST_CTL
#define DEBUG_UART_BUART_sRX_RxBitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB10_MSK_ACTL
#define DEBUG_UART_BUART_sRX_RxBitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB10_MSK_ACTL
#define DEBUG_UART_BUART_sRX_RxBitCounter__PERIOD_REG CYREG_B1_UDB10_MSK
#define DEBUG_UART_BUART_sRX_RxBitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB10_11_ACTL
#define DEBUG_UART_BUART_sRX_RxBitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB10_11_ST
#define DEBUG_UART_BUART_sRX_RxBitCounter_ST__MASK_REG CYREG_B1_UDB10_MSK
#define DEBUG_UART_BUART_sRX_RxBitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB10_MSK_ACTL
#define DEBUG_UART_BUART_sRX_RxBitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB10_MSK_ACTL
#define DEBUG_UART_BUART_sRX_RxBitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB10_ACTL
#define DEBUG_UART_BUART_sRX_RxBitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB10_ST_CTL
#define DEBUG_UART_BUART_sRX_RxBitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB10_ST_CTL
#define DEBUG_UART_BUART_sRX_RxBitCounter_ST__STATUS_REG CYREG_B1_UDB10_ST
#define DEBUG_UART_BUART_sRX_RxShifter_u0__16BIT_A0_REG CYREG_B0_UDB08_09_A0
#define DEBUG_UART_BUART_sRX_RxShifter_u0__16BIT_A1_REG CYREG_B0_UDB08_09_A1
#define DEBUG_UART_BUART_sRX_RxShifter_u0__16BIT_D0_REG CYREG_B0_UDB08_09_D0
#define DEBUG_UART_BUART_sRX_RxShifter_u0__16BIT_D1_REG CYREG_B0_UDB08_09_D1
#define DEBUG_UART_BUART_sRX_RxShifter_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL
#define DEBUG_UART_BUART_sRX_RxShifter_u0__16BIT_F0_REG CYREG_B0_UDB08_09_F0
#define DEBUG_UART_BUART_sRX_RxShifter_u0__16BIT_F1_REG CYREG_B0_UDB08_09_F1
#define DEBUG_UART_BUART_sRX_RxShifter_u0__A0_A1_REG CYREG_B0_UDB08_A0_A1
#define DEBUG_UART_BUART_sRX_RxShifter_u0__A0_REG CYREG_B0_UDB08_A0
#define DEBUG_UART_BUART_sRX_RxShifter_u0__A1_REG CYREG_B0_UDB08_A1
#define DEBUG_UART_BUART_sRX_RxShifter_u0__D0_D1_REG CYREG_B0_UDB08_D0_D1
#define DEBUG_UART_BUART_sRX_RxShifter_u0__D0_REG CYREG_B0_UDB08_D0
#define DEBUG_UART_BUART_sRX_RxShifter_u0__D1_REG CYREG_B0_UDB08_D1
#define DEBUG_UART_BUART_sRX_RxShifter_u0__DP_AUX_CTL_REG CYREG_B0_UDB08_ACTL
#define DEBUG_UART_BUART_sRX_RxShifter_u0__F0_F1_REG CYREG_B0_UDB08_F0_F1
#define DEBUG_UART_BUART_sRX_RxShifter_u0__F0_REG CYREG_B0_UDB08_F0
#define DEBUG_UART_BUART_sRX_RxShifter_u0__F1_REG CYREG_B0_UDB08_F1
#define DEBUG_UART_BUART_sRX_RxSts__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL
#define DEBUG_UART_BUART_sRX_RxSts__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST
#define DEBUG_UART_BUART_sRX_RxSts__3__MASK 0x08u
#define DEBUG_UART_BUART_sRX_RxSts__3__POS 3
#define DEBUG_UART_BUART_sRX_RxSts__4__MASK 0x10u
#define DEBUG_UART_BUART_sRX_RxSts__4__POS 4
#define DEBUG_UART_BUART_sRX_RxSts__5__MASK 0x20u
#define DEBUG_UART_BUART_sRX_RxSts__5__POS 5
#define DEBUG_UART_BUART_sRX_RxSts__MASK 0x38u
#define DEBUG_UART_BUART_sRX_RxSts__MASK_REG CYREG_B0_UDB07_MSK
#define DEBUG_UART_BUART_sRX_RxSts__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL
#define DEBUG_UART_BUART_sRX_RxSts__STATUS_REG CYREG_B0_UDB07_ST
#define DEBUG_UART_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_A0_REG CYREG_B0_UDB04_05_A0
#define DEBUG_UART_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_A1_REG CYREG_B0_UDB04_05_A1
#define DEBUG_UART_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_D0_REG CYREG_B0_UDB04_05_D0
#define DEBUG_UART_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_D1_REG CYREG_B0_UDB04_05_D1
#define DEBUG_UART_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
#define DEBUG_UART_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_F0_REG CYREG_B0_UDB04_05_F0
#define DEBUG_UART_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_F1_REG CYREG_B0_UDB04_05_F1
#define DEBUG_UART_BUART_sTX_sCLOCK_TxBitClkGen__A0_A1_REG CYREG_B0_UDB04_A0_A1
#define DEBUG_UART_BUART_sTX_sCLOCK_TxBitClkGen__A0_REG CYREG_B0_UDB04_A0
#define DEBUG_UART_BUART_sTX_sCLOCK_TxBitClkGen__A1_REG CYREG_B0_UDB04_A1
#define DEBUG_UART_BUART_sTX_sCLOCK_TxBitClkGen__D0_D1_REG CYREG_B0_UDB04_D0_D1
#define DEBUG_UART_BUART_sTX_sCLOCK_TxBitClkGen__D0_REG CYREG_B0_UDB04_D0
#define DEBUG_UART_BUART_sTX_sCLOCK_TxBitClkGen__D1_REG CYREG_B0_UDB04_D1
#define DEBUG_UART_BUART_sTX_sCLOCK_TxBitClkGen__DP_AUX_CTL_REG CYREG_B0_UDB04_ACTL
#define DEBUG_UART_BUART_sTX_sCLOCK_TxBitClkGen__F0_F1_REG CYREG_B0_UDB04_F0_F1
#define DEBUG_UART_BUART_sTX_sCLOCK_TxBitClkGen__F0_REG CYREG_B0_UDB04_F0
#define DEBUG_UART_BUART_sTX_sCLOCK_TxBitClkGen__F1_REG CYREG_B0_UDB04_F1
#define DEBUG_UART_BUART_sTX_TxShifter_u0__16BIT_A0_REG CYREG_B0_UDB03_04_A0
#define DEBUG_UART_BUART_sTX_TxShifter_u0__16BIT_A1_REG CYREG_B0_UDB03_04_A1
#define DEBUG_UART_BUART_sTX_TxShifter_u0__16BIT_D0_REG CYREG_B0_UDB03_04_D0
#define DEBUG_UART_BUART_sTX_TxShifter_u0__16BIT_D1_REG CYREG_B0_UDB03_04_D1
#define DEBUG_UART_BUART_sTX_TxShifter_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL
#define DEBUG_UART_BUART_sTX_TxShifter_u0__16BIT_F0_REG CYREG_B0_UDB03_04_F0
#define DEBUG_UART_BUART_sTX_TxShifter_u0__16BIT_F1_REG CYREG_B0_UDB03_04_F1
#define DEBUG_UART_BUART_sTX_TxShifter_u0__A0_A1_REG CYREG_B0_UDB03_A0_A1
#define DEBUG_UART_BUART_sTX_TxShifter_u0__A0_REG CYREG_B0_UDB03_A0
#define DEBUG_UART_BUART_sTX_TxShifter_u0__A1_REG CYREG_B0_UDB03_A1
#define DEBUG_UART_BUART_sTX_TxShifter_u0__D0_D1_REG CYREG_B0_UDB03_D0_D1
#define DEBUG_UART_BUART_sTX_TxShifter_u0__D0_REG CYREG_B0_UDB03_D0
#define DEBUG_UART_BUART_sTX_TxShifter_u0__D1_REG CYREG_B0_UDB03_D1
#define DEBUG_UART_BUART_sTX_TxShifter_u0__DP_AUX_CTL_REG CYREG_B0_UDB03_ACTL
#define DEBUG_UART_BUART_sTX_TxShifter_u0__F0_F1_REG CYREG_B0_UDB03_F0_F1
#define DEBUG_UART_BUART_sTX_TxShifter_u0__F0_REG CYREG_B0_UDB03_F0
#define DEBUG_UART_BUART_sTX_TxShifter_u0__F1_REG CYREG_B0_UDB03_F1
#define DEBUG_UART_BUART_sTX_TxSts__0__MASK 0x01u
#define DEBUG_UART_BUART_sTX_TxSts__0__POS 0
#define DEBUG_UART_BUART_sTX_TxSts__1__MASK 0x02u
#define DEBUG_UART_BUART_sTX_TxSts__1__POS 1
#define DEBUG_UART_BUART_sTX_TxSts__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL
#define DEBUG_UART_BUART_sTX_TxSts__16BIT_STATUS_REG CYREG_B0_UDB03_04_ST
#define DEBUG_UART_BUART_sTX_TxSts__2__MASK 0x04u
#define DEBUG_UART_BUART_sTX_TxSts__2__POS 2
#define DEBUG_UART_BUART_sTX_TxSts__3__MASK 0x08u
#define DEBUG_UART_BUART_sTX_TxSts__3__POS 3
#define DEBUG_UART_BUART_sTX_TxSts__MASK 0x0Fu
#define DEBUG_UART_BUART_sTX_TxSts__MASK_REG CYREG_B0_UDB03_MSK
#define DEBUG_UART_BUART_sTX_TxSts__STATUS_AUX_CTL_REG CYREG_B0_UDB03_ACTL
#define DEBUG_UART_BUART_sTX_TxSts__STATUS_REG CYREG_B0_UDB03_ST

/* DEBUG_UART_IntClock */
#define DEBUG_UART_IntClock__CFG0 CYREG_CLKDIST_DCFG1_CFG0
#define DEBUG_UART_IntClock__CFG1 CYREG_CLKDIST_DCFG1_CFG1
#define DEBUG_UART_IntClock__CFG2 CYREG_CLKDIST_DCFG1_CFG2
#define DEBUG_UART_IntClock__CFG2_SRC_SEL_MASK 0x07u
#define DEBUG_UART_IntClock__INDEX 0x01u
#define DEBUG_UART_IntClock__PM_ACT_CFG CYREG_PM_ACT_CFG2
#define DEBUG_UART_IntClock__PM_ACT_MSK 0x02u
#define DEBUG_UART_IntClock__PM_STBY_CFG CYREG_PM_STBY_CFG2
#define DEBUG_UART_IntClock__PM_STBY_MSK 0x02u

/* Out_1 */
#define Out_1__0__INTTYPE CYREG_PICU15_INTTYPE0
#define Out_1__0__MASK 0x01u
#define Out_1__0__PC CYREG_IO_PC_PRT15_PC0
#define Out_1__0__PORT 15u
#define Out_1__0__SHIFT 0u
#define Out_1__AG CYREG_PRT15_AG
#define Out_1__AMUX CYREG_PRT15_AMUX
#define Out_1__BIE CYREG_PRT15_BIE
#define Out_1__BIT_MASK CYREG_PRT15_BIT_MASK
#define Out_1__BYP CYREG_PRT15_BYP
#define Out_1__CTL CYREG_PRT15_CTL
#define Out_1__DM0 CYREG_PRT15_DM0
#define Out_1__DM1 CYREG_PRT15_DM1
#define Out_1__DM2 CYREG_PRT15_DM2
#define Out_1__DR CYREG_PRT15_DR
#define Out_1__INP_DIS CYREG_PRT15_INP_DIS
#define Out_1__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE
#define Out_1__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
#define Out_1__LCD_EN CYREG_PRT15_LCD_EN
#define Out_1__MASK 0x01u
#define Out_1__PORT 15u
#define Out_1__PRT CYREG_PRT15_PRT
#define Out_1__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
#define Out_1__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
#define Out_1__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
#define Out_1__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
#define Out_1__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
#define Out_1__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
#define Out_1__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
#define Out_1__PS CYREG_PRT15_PS
#define Out_1__SHIFT 0u
#define Out_1__SLW CYREG_PRT15_SLW
#define Out_10__0__INTTYPE CYREG_PICU12_INTTYPE5
#define Out_10__0__MASK 0x20u
#define Out_10__0__PC CYREG_PRT12_PC5
#define Out_10__0__PORT 12u
#define Out_10__0__SHIFT 5u
#define Out_10__AG CYREG_PRT12_AG
#define Out_10__BIE CYREG_PRT12_BIE
#define Out_10__BIT_MASK CYREG_PRT12_BIT_MASK
#define Out_10__BYP CYREG_PRT12_BYP
#define Out_10__DM0 CYREG_PRT12_DM0
#define Out_10__DM1 CYREG_PRT12_DM1
#define Out_10__DM2 CYREG_PRT12_DM2
#define Out_10__DR CYREG_PRT12_DR
#define Out_10__INP_DIS CYREG_PRT12_INP_DIS
#define Out_10__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU12_BASE
#define Out_10__MASK 0x20u
#define Out_10__PORT 12u
#define Out_10__PRT CYREG_PRT12_PRT
#define Out_10__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
#define Out_10__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
#define Out_10__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
#define Out_10__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
#define Out_10__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
#define Out_10__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
#define Out_10__PS CYREG_PRT12_PS
#define Out_10__SHIFT 5u
#define Out_10__SIO_CFG CYREG_PRT12_SIO_CFG
#define Out_10__SIO_DIFF CYREG_PRT12_SIO_DIFF
#define Out_10__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
#define Out_10__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
#define Out_10__SLW CYREG_PRT12_SLW

/* Out_2 */
#define Out_2__0__INTTYPE CYREG_PICU15_INTTYPE1
#define Out_2__0__MASK 0x02u
#define Out_2__0__PC CYREG_IO_PC_PRT15_PC1
#define Out_2__0__PORT 15u
#define Out_2__0__SHIFT 1u
#define Out_2__AG CYREG_PRT15_AG
#define Out_2__AMUX CYREG_PRT15_AMUX
#define Out_2__BIE CYREG_PRT15_BIE
#define Out_2__BIT_MASK CYREG_PRT15_BIT_MASK
#define Out_2__BYP CYREG_PRT15_BYP
#define Out_2__CTL CYREG_PRT15_CTL
#define Out_2__DM0 CYREG_PRT15_DM0
#define Out_2__DM1 CYREG_PRT15_DM1
#define Out_2__DM2 CYREG_PRT15_DM2
#define Out_2__DR CYREG_PRT15_DR
#define Out_2__INP_DIS CYREG_PRT15_INP_DIS
#define Out_2__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE
#define Out_2__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
#define Out_2__LCD_EN CYREG_PRT15_LCD_EN
#define Out_2__MASK 0x02u
#define Out_2__PORT 15u
#define Out_2__PRT CYREG_PRT15_PRT
#define Out_2__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
#define Out_2__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
#define Out_2__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
#define Out_2__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
#define Out_2__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
#define Out_2__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
#define Out_2__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
#define Out_2__PS CYREG_PRT15_PS
#define Out_2__SHIFT 1u
#define Out_2__SLW CYREG_PRT15_SLW

/* Out_3 */
#define Out_3__0__INTTYPE CYREG_PICU15_INTTYPE2
#define Out_3__0__MASK 0x04u
#define Out_3__0__PC CYREG_IO_PC_PRT15_PC2
#define Out_3__0__PORT 15u
#define Out_3__0__SHIFT 2u
#define Out_3__AG CYREG_PRT15_AG
#define Out_3__AMUX CYREG_PRT15_AMUX
#define Out_3__BIE CYREG_PRT15_BIE
#define Out_3__BIT_MASK CYREG_PRT15_BIT_MASK
#define Out_3__BYP CYREG_PRT15_BYP
#define Out_3__CTL CYREG_PRT15_CTL
#define Out_3__DM0 CYREG_PRT15_DM0
#define Out_3__DM1 CYREG_PRT15_DM1
#define Out_3__DM2 CYREG_PRT15_DM2
#define Out_3__DR CYREG_PRT15_DR
#define Out_3__INP_DIS CYREG_PRT15_INP_DIS
#define Out_3__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE
#define Out_3__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
#define Out_3__LCD_EN CYREG_PRT15_LCD_EN
#define Out_3__MASK 0x04u
#define Out_3__PORT 15u
#define Out_3__PRT CYREG_PRT15_PRT
#define Out_3__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
#define Out_3__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
#define Out_3__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
#define Out_3__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
#define Out_3__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
#define Out_3__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
#define Out_3__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
#define Out_3__PS CYREG_PRT15_PS
#define Out_3__SHIFT 2u
#define Out_3__SLW CYREG_PRT15_SLW

/* Out_4 */
#define Out_4__0__INTTYPE CYREG_PICU15_INTTYPE3
#define Out_4__0__MASK 0x08u
#define Out_4__0__PC CYREG_IO_PC_PRT15_PC3
#define Out_4__0__PORT 15u
#define Out_4__0__SHIFT 3u
#define Out_4__AG CYREG_PRT15_AG
#define Out_4__AMUX CYREG_PRT15_AMUX
#define Out_4__BIE CYREG_PRT15_BIE
#define Out_4__BIT_MASK CYREG_PRT15_BIT_MASK
#define Out_4__BYP CYREG_PRT15_BYP
#define Out_4__CTL CYREG_PRT15_CTL
#define Out_4__DM0 CYREG_PRT15_DM0
#define Out_4__DM1 CYREG_PRT15_DM1
#define Out_4__DM2 CYREG_PRT15_DM2
#define Out_4__DR CYREG_PRT15_DR
#define Out_4__INP_DIS CYREG_PRT15_INP_DIS
#define Out_4__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE
#define Out_4__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
#define Out_4__LCD_EN CYREG_PRT15_LCD_EN
#define Out_4__MASK 0x08u
#define Out_4__PORT 15u
#define Out_4__PRT CYREG_PRT15_PRT
#define Out_4__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
#define Out_4__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
#define Out_4__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
#define Out_4__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
#define Out_4__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
#define Out_4__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
#define Out_4__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
#define Out_4__PS CYREG_PRT15_PS
#define Out_4__SHIFT 3u
#define Out_4__SLW CYREG_PRT15_SLW

/* Out_5 */
#define Out_5__0__INTTYPE CYREG_PICU15_INTTYPE4
#define Out_5__0__MASK 0x10u
#define Out_5__0__PC CYREG_IO_PC_PRT15_PC4
#define Out_5__0__PORT 15u
#define Out_5__0__SHIFT 4u
#define Out_5__AG CYREG_PRT15_AG
#define Out_5__AMUX CYREG_PRT15_AMUX
#define Out_5__BIE CYREG_PRT15_BIE
#define Out_5__BIT_MASK CYREG_PRT15_BIT_MASK
#define Out_5__BYP CYREG_PRT15_BYP
#define Out_5__CTL CYREG_PRT15_CTL
#define Out_5__DM0 CYREG_PRT15_DM0
#define Out_5__DM1 CYREG_PRT15_DM1
#define Out_5__DM2 CYREG_PRT15_DM2
#define Out_5__DR CYREG_PRT15_DR
#define Out_5__INP_DIS CYREG_PRT15_INP_DIS
#define Out_5__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE
#define Out_5__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
#define Out_5__LCD_EN CYREG_PRT15_LCD_EN
#define Out_5__MASK 0x10u
#define Out_5__PORT 15u
#define Out_5__PRT CYREG_PRT15_PRT
#define Out_5__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
#define Out_5__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
#define Out_5__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
#define Out_5__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
#define Out_5__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
#define Out_5__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
#define Out_5__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
#define Out_5__PS CYREG_PRT15_PS
#define Out_5__SHIFT 4u
#define Out_5__SLW CYREG_PRT15_SLW

/* Out_6 */
#define Out_6__0__INTTYPE CYREG_PICU15_INTTYPE5
#define Out_6__0__MASK 0x20u
#define Out_6__0__PC CYREG_IO_PC_PRT15_PC5
#define Out_6__0__PORT 15u
#define Out_6__0__SHIFT 5u
#define Out_6__AG CYREG_PRT15_AG
#define Out_6__AMUX CYREG_PRT15_AMUX
#define Out_6__BIE CYREG_PRT15_BIE
#define Out_6__BIT_MASK CYREG_PRT15_BIT_MASK
#define Out_6__BYP CYREG_PRT15_BYP
#define Out_6__CTL CYREG_PRT15_CTL
#define Out_6__DM0 CYREG_PRT15_DM0
#define Out_6__DM1 CYREG_PRT15_DM1
#define Out_6__DM2 CYREG_PRT15_DM2
#define Out_6__DR CYREG_PRT15_DR
#define Out_6__INP_DIS CYREG_PRT15_INP_DIS
#define Out_6__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE
#define Out_6__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
#define Out_6__LCD_EN CYREG_PRT15_LCD_EN
#define Out_6__MASK 0x20u
#define Out_6__PORT 15u
#define Out_6__PRT CYREG_PRT15_PRT
#define Out_6__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
#define Out_6__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
#define Out_6__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
#define Out_6__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
#define Out_6__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
#define Out_6__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
#define Out_6__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
#define Out_6__PS CYREG_PRT15_PS
#define Out_6__SHIFT 5u
#define Out_6__SLW CYREG_PRT15_SLW

/* Out_7 */
#define Out_7__0__INTTYPE CYREG_PICU12_INTTYPE2
#define Out_7__0__MASK 0x04u
#define Out_7__0__PC CYREG_PRT12_PC2
#define Out_7__0__PORT 12u
#define Out_7__0__SHIFT 2u
#define Out_7__AG CYREG_PRT12_AG
#define Out_7__BIE CYREG_PRT12_BIE
#define Out_7__BIT_MASK CYREG_PRT12_BIT_MASK
#define Out_7__BYP CYREG_PRT12_BYP
#define Out_7__DM0 CYREG_PRT12_DM0
#define Out_7__DM1 CYREG_PRT12_DM1
#define Out_7__DM2 CYREG_PRT12_DM2
#define Out_7__DR CYREG_PRT12_DR
#define Out_7__INP_DIS CYREG_PRT12_INP_DIS
#define Out_7__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU12_BASE
#define Out_7__MASK 0x04u
#define Out_7__PORT 12u
#define Out_7__PRT CYREG_PRT12_PRT
#define Out_7__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
#define Out_7__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
#define Out_7__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
#define Out_7__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
#define Out_7__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
#define Out_7__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
#define Out_7__PS CYREG_PRT12_PS
#define Out_7__SHIFT 2u
#define Out_7__SIO_CFG CYREG_PRT12_SIO_CFG
#define Out_7__SIO_DIFF CYREG_PRT12_SIO_DIFF
#define Out_7__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
#define Out_7__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
#define Out_7__SLW CYREG_PRT12_SLW

/* Out_8 */
#define Out_8__0__INTTYPE CYREG_PICU12_INTTYPE3
#define Out_8__0__MASK 0x08u
#define Out_8__0__PC CYREG_PRT12_PC3
#define Out_8__0__PORT 12u
#define Out_8__0__SHIFT 3u
#define Out_8__AG CYREG_PRT12_AG
#define Out_8__BIE CYREG_PRT12_BIE
#define Out_8__BIT_MASK CYREG_PRT12_BIT_MASK
#define Out_8__BYP CYREG_PRT12_BYP
#define Out_8__DM0 CYREG_PRT12_DM0
#define Out_8__DM1 CYREG_PRT12_DM1
#define Out_8__DM2 CYREG_PRT12_DM2
#define Out_8__DR CYREG_PRT12_DR
#define Out_8__INP_DIS CYREG_PRT12_INP_DIS
#define Out_8__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU12_BASE
#define Out_8__MASK 0x08u
#define Out_8__PORT 12u
#define Out_8__PRT CYREG_PRT12_PRT
#define Out_8__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
#define Out_8__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
#define Out_8__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
#define Out_8__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
#define Out_8__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
#define Out_8__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
#define Out_8__PS CYREG_PRT12_PS
#define Out_8__SHIFT 3u
#define Out_8__SIO_CFG CYREG_PRT12_SIO_CFG
#define Out_8__SIO_DIFF CYREG_PRT12_SIO_DIFF
#define Out_8__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
#define Out_8__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
#define Out_8__SLW CYREG_PRT12_SLW

/* Out_9 */
#define Out_9__0__INTTYPE CYREG_PICU12_INTTYPE4
#define Out_9__0__MASK 0x10u
#define Out_9__0__PC CYREG_PRT12_PC4
#define Out_9__0__PORT 12u
#define Out_9__0__SHIFT 4u
#define Out_9__AG CYREG_PRT12_AG
#define Out_9__BIE CYREG_PRT12_BIE
#define Out_9__BIT_MASK CYREG_PRT12_BIT_MASK
#define Out_9__BYP CYREG_PRT12_BYP
#define Out_9__DM0 CYREG_PRT12_DM0
#define Out_9__DM1 CYREG_PRT12_DM1
#define Out_9__DM2 CYREG_PRT12_DM2
#define Out_9__DR CYREG_PRT12_DR
#define Out_9__INP_DIS CYREG_PRT12_INP_DIS
#define Out_9__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU12_BASE
#define Out_9__MASK 0x10u
#define Out_9__PORT 12u
#define Out_9__PRT CYREG_PRT12_PRT
#define Out_9__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
#define Out_9__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
#define Out_9__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
#define Out_9__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
#define Out_9__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
#define Out_9__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
#define Out_9__PS CYREG_PRT12_PS
#define Out_9__SHIFT 4u
#define Out_9__SIO_CFG CYREG_PRT12_SIO_CFG
#define Out_9__SIO_DIFF CYREG_PRT12_SIO_DIFF
#define Out_9__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
#define Out_9__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
#define Out_9__SLW CYREG_PRT12_SLW

/* OutputReg1 */
#define OutputReg1_Sync_ctrl_reg__0__MASK 0x01u
#define OutputReg1_Sync_ctrl_reg__0__POS 0
#define OutputReg1_Sync_ctrl_reg__1__MASK 0x02u
#define OutputReg1_Sync_ctrl_reg__1__POS 1
#define OutputReg1_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL
#define OutputReg1_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB05_06_CTL
#define OutputReg1_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB05_06_CTL
#define OutputReg1_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB05_06_CTL
#define OutputReg1_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB05_06_CTL
#define OutputReg1_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB05_06_MSK
#define OutputReg1_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB05_06_MSK
#define OutputReg1_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB05_06_MSK
#define OutputReg1_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB05_06_MSK
#define OutputReg1_Sync_ctrl_reg__2__MASK 0x04u
#define OutputReg1_Sync_ctrl_reg__2__POS 2
#define OutputReg1_Sync_ctrl_reg__3__MASK 0x08u
#define OutputReg1_Sync_ctrl_reg__3__POS 3
#define OutputReg1_Sync_ctrl_reg__4__MASK 0x10u
#define OutputReg1_Sync_ctrl_reg__4__POS 4
#define OutputReg1_Sync_ctrl_reg__5__MASK 0x20u
#define OutputReg1_Sync_ctrl_reg__5__POS 5
#define OutputReg1_Sync_ctrl_reg__6__MASK 0x40u
#define OutputReg1_Sync_ctrl_reg__6__POS 6
#define OutputReg1_Sync_ctrl_reg__7__MASK 0x80u
#define OutputReg1_Sync_ctrl_reg__7__POS 7
#define OutputReg1_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB05_ACTL
#define OutputReg1_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB05_CTL
#define OutputReg1_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB05_ST_CTL
#define OutputReg1_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB05_CTL
#define OutputReg1_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB05_ST_CTL
#define OutputReg1_Sync_ctrl_reg__MASK 0xFFu
#define OutputReg1_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL
#define OutputReg1_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL
#define OutputReg1_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB05_MSK

/* OutputReg2 */
#define OutputReg2_Sync_ctrl_reg__0__MASK 0x01u
#define OutputReg2_Sync_ctrl_reg__0__POS 0
#define OutputReg2_Sync_ctrl_reg__1__MASK 0x02u
#define OutputReg2_Sync_ctrl_reg__1__POS 1
#define OutputReg2_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL
#define OutputReg2_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB10_11_CTL
#define OutputReg2_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB10_11_CTL
#define OutputReg2_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB10_11_CTL
#define OutputReg2_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB10_11_CTL
#define OutputReg2_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB10_11_MSK
#define OutputReg2_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB10_11_MSK
#define OutputReg2_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB10_11_MSK
#define OutputReg2_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB10_11_MSK
#define OutputReg2_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB10_ACTL
#define OutputReg2_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB10_CTL
#define OutputReg2_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB10_ST_CTL
#define OutputReg2_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB10_CTL
#define OutputReg2_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB10_ST_CTL
#define OutputReg2_Sync_ctrl_reg__MASK 0x03u
#define OutputReg2_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL
#define OutputReg2_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL
#define OutputReg2_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB10_MSK

/* Rx_1 */
#define Rx_1__0__INTTYPE CYREG_PICU12_INTTYPE6
#define Rx_1__0__MASK 0x40u
#define Rx_1__0__PC CYREG_PRT12_PC6
#define Rx_1__0__PORT 12u
#define Rx_1__0__SHIFT 6u
#define Rx_1__AG CYREG_PRT12_AG
#define Rx_1__BIE CYREG_PRT12_BIE
#define Rx_1__BIT_MASK CYREG_PRT12_BIT_MASK
#define Rx_1__BYP CYREG_PRT12_BYP
#define Rx_1__DM0 CYREG_PRT12_DM0
#define Rx_1__DM1 CYREG_PRT12_DM1
#define Rx_1__DM2 CYREG_PRT12_DM2
#define Rx_1__DR CYREG_PRT12_DR
#define Rx_1__INP_DIS CYREG_PRT12_INP_DIS
#define Rx_1__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU12_BASE
#define Rx_1__MASK 0x40u
#define Rx_1__PORT 12u
#define Rx_1__PRT CYREG_PRT12_PRT
#define Rx_1__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
#define Rx_1__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
#define Rx_1__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
#define Rx_1__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
#define Rx_1__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
#define Rx_1__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
#define Rx_1__PS CYREG_PRT12_PS
#define Rx_1__SHIFT 6u
#define Rx_1__SIO_CFG CYREG_PRT12_SIO_CFG
#define Rx_1__SIO_DIFF CYREG_PRT12_SIO_DIFF
#define Rx_1__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
#define Rx_1__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
#define Rx_1__SLW CYREG_PRT12_SLW

/* Tx_1 */
#define Tx_1__0__INTTYPE CYREG_PICU12_INTTYPE7
#define Tx_1__0__MASK 0x80u
#define Tx_1__0__PC CYREG_PRT12_PC7
#define Tx_1__0__PORT 12u
#define Tx_1__0__SHIFT 7u
#define Tx_1__AG CYREG_PRT12_AG
#define Tx_1__BIE CYREG_PRT12_BIE
#define Tx_1__BIT_MASK CYREG_PRT12_BIT_MASK
#define Tx_1__BYP CYREG_PRT12_BYP
#define Tx_1__DM0 CYREG_PRT12_DM0
#define Tx_1__DM1 CYREG_PRT12_DM1
#define Tx_1__DM2 CYREG_PRT12_DM2
#define Tx_1__DR CYREG_PRT12_DR
#define Tx_1__INP_DIS CYREG_PRT12_INP_DIS
#define Tx_1__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU12_BASE
#define Tx_1__MASK 0x80u
#define Tx_1__PORT 12u
#define Tx_1__PRT CYREG_PRT12_PRT
#define Tx_1__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
#define Tx_1__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
#define Tx_1__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
#define Tx_1__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
#define Tx_1__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
#define Tx_1__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
#define Tx_1__PS CYREG_PRT12_PS
#define Tx_1__SHIFT 7u
#define Tx_1__SIO_CFG CYREG_PRT12_SIO_CFG
#define Tx_1__SIO_DIFF CYREG_PRT12_SIO_DIFF
#define Tx_1__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
#define Tx_1__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
#define Tx_1__SLW CYREG_PRT12_SLW

/* USBFS_1 */
#define USBFS_1_arb_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define USBFS_1_arb_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
#define USBFS_1_arb_int__INTC_MASK 0x400000u
#define USBFS_1_arb_int__INTC_NUMBER 22u
#define USBFS_1_arb_int__INTC_PRIOR_NUM 7u
#define USBFS_1_arb_int__INTC_PRIOR_REG CYREG_NVIC_PRI_22
#define USBFS_1_arb_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define USBFS_1_arb_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
#define USBFS_1_bus_reset__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define USBFS_1_bus_reset__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
#define USBFS_1_bus_reset__INTC_MASK 0x800000u
#define USBFS_1_bus_reset__INTC_NUMBER 23u
#define USBFS_1_bus_reset__INTC_PRIOR_NUM 7u
#define USBFS_1_bus_reset__INTC_PRIOR_REG CYREG_NVIC_PRI_23
#define USBFS_1_bus_reset__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define USBFS_1_bus_reset__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
#define USBFS_1_Dm__0__INTTYPE CYREG_PICU15_INTTYPE7
#define USBFS_1_Dm__0__MASK 0x80u
#define USBFS_1_Dm__0__PC CYREG_IO_PC_PRT15_7_6_PC1
#define USBFS_1_Dm__0__PORT 15u
#define USBFS_1_Dm__0__SHIFT 7u
#define USBFS_1_Dm__AG CYREG_PRT15_AG
#define USBFS_1_Dm__AMUX CYREG_PRT15_AMUX
#define USBFS_1_Dm__BIE CYREG_PRT15_BIE
#define USBFS_1_Dm__BIT_MASK CYREG_PRT15_BIT_MASK
#define USBFS_1_Dm__BYP CYREG_PRT15_BYP
#define USBFS_1_Dm__CTL CYREG_PRT15_CTL
#define USBFS_1_Dm__DM0 CYREG_PRT15_DM0
#define USBFS_1_Dm__DM1 CYREG_PRT15_DM1
#define USBFS_1_Dm__DM2 CYREG_PRT15_DM2
#define USBFS_1_Dm__DR CYREG_PRT15_DR
#define USBFS_1_Dm__INP_DIS CYREG_PRT15_INP_DIS
#define USBFS_1_Dm__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE
#define USBFS_1_Dm__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
#define USBFS_1_Dm__LCD_EN CYREG_PRT15_LCD_EN
#define USBFS_1_Dm__MASK 0x80u
#define USBFS_1_Dm__PORT 15u
#define USBFS_1_Dm__PRT CYREG_PRT15_PRT
#define USBFS_1_Dm__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
#define USBFS_1_Dm__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
#define USBFS_1_Dm__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
#define USBFS_1_Dm__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
#define USBFS_1_Dm__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
#define USBFS_1_Dm__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
#define USBFS_1_Dm__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
#define USBFS_1_Dm__PS CYREG_PRT15_PS
#define USBFS_1_Dm__SHIFT 7u
#define USBFS_1_Dm__SLW CYREG_PRT15_SLW
#define USBFS_1_Dp__0__INTTYPE CYREG_PICU15_INTTYPE6
#define USBFS_1_Dp__0__MASK 0x40u
#define USBFS_1_Dp__0__PC CYREG_IO_PC_PRT15_7_6_PC0
#define USBFS_1_Dp__0__PORT 15u
#define USBFS_1_Dp__0__SHIFT 6u
#define USBFS_1_Dp__AG CYREG_PRT15_AG
#define USBFS_1_Dp__AMUX CYREG_PRT15_AMUX
#define USBFS_1_Dp__BIE CYREG_PRT15_BIE
#define USBFS_1_Dp__BIT_MASK CYREG_PRT15_BIT_MASK
#define USBFS_1_Dp__BYP CYREG_PRT15_BYP
#define USBFS_1_Dp__CTL CYREG_PRT15_CTL
#define USBFS_1_Dp__DM0 CYREG_PRT15_DM0
#define USBFS_1_Dp__DM1 CYREG_PRT15_DM1
#define USBFS_1_Dp__DM2 CYREG_PRT15_DM2
#define USBFS_1_Dp__DR CYREG_PRT15_DR
#define USBFS_1_Dp__INP_DIS CYREG_PRT15_INP_DIS
#define USBFS_1_Dp__INTSTAT CYREG_PICU15_INTSTAT
#define USBFS_1_Dp__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE
#define USBFS_1_Dp__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
#define USBFS_1_Dp__LCD_EN CYREG_PRT15_LCD_EN
#define USBFS_1_Dp__MASK 0x40u
#define USBFS_1_Dp__PORT 15u
#define USBFS_1_Dp__PRT CYREG_PRT15_PRT
#define USBFS_1_Dp__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
#define USBFS_1_Dp__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
#define USBFS_1_Dp__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
#define USBFS_1_Dp__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
#define USBFS_1_Dp__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
#define USBFS_1_Dp__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
#define USBFS_1_Dp__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
#define USBFS_1_Dp__PS CYREG_PRT15_PS
#define USBFS_1_Dp__SHIFT 6u
#define USBFS_1_Dp__SLW CYREG_PRT15_SLW
#define USBFS_1_Dp__SNAP CYREG_PICU_15_SNAP_15
#define USBFS_1_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define USBFS_1_dp_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
#define USBFS_1_dp_int__INTC_MASK 0x1000u
#define USBFS_1_dp_int__INTC_NUMBER 12u
#define USBFS_1_dp_int__INTC_PRIOR_NUM 7u
#define USBFS_1_dp_int__INTC_PRIOR_REG CYREG_NVIC_PRI_12
#define USBFS_1_dp_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define USBFS_1_dp_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
#define USBFS_1_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define USBFS_1_ep_0__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
#define USBFS_1_ep_0__INTC_MASK 0x1000000u
#define USBFS_1_ep_0__INTC_NUMBER 24u
#define USBFS_1_ep_0__INTC_PRIOR_NUM 7u
#define USBFS_1_ep_0__INTC_PRIOR_REG CYREG_NVIC_PRI_24
#define USBFS_1_ep_0__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define USBFS_1_ep_0__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
#define USBFS_1_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define USBFS_1_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
#define USBFS_1_ep_1__INTC_MASK 0x02u
#define USBFS_1_ep_1__INTC_NUMBER 1u
#define USBFS_1_ep_1__INTC_PRIOR_NUM 7u
#define USBFS_1_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_1
#define USBFS_1_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define USBFS_1_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
#define USBFS_1_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define USBFS_1_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
#define USBFS_1_ep_2__INTC_MASK 0x04u
#define USBFS_1_ep_2__INTC_NUMBER 2u
#define USBFS_1_ep_2__INTC_PRIOR_NUM 7u
#define USBFS_1_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_2
#define USBFS_1_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define USBFS_1_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
#define USBFS_1_ord_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define USBFS_1_ord_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
#define USBFS_1_ord_int__INTC_MASK 0x2000000u
#define USBFS_1_ord_int__INTC_NUMBER 25u
#define USBFS_1_ord_int__INTC_PRIOR_NUM 7u
#define USBFS_1_ord_int__INTC_PRIOR_REG CYREG_NVIC_PRI_25
#define USBFS_1_ord_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define USBFS_1_ord_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
#define USBFS_1_sof_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define USBFS_1_sof_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
#define USBFS_1_sof_int__INTC_MASK 0x200000u
#define USBFS_1_sof_int__INTC_NUMBER 21u
#define USBFS_1_sof_int__INTC_PRIOR_NUM 7u
#define USBFS_1_sof_int__INTC_PRIOR_REG CYREG_NVIC_PRI_21
#define USBFS_1_sof_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define USBFS_1_sof_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
#define USBFS_1_USB__ARB_CFG CYREG_USB_ARB_CFG
#define USBFS_1_USB__ARB_EP1_CFG CYREG_USB_ARB_EP1_CFG
#define USBFS_1_USB__ARB_EP1_INT_EN CYREG_USB_ARB_EP1_INT_EN
#define USBFS_1_USB__ARB_EP1_SR CYREG_USB_ARB_EP1_SR
#define USBFS_1_USB__ARB_EP2_CFG CYREG_USB_ARB_EP2_CFG
#define USBFS_1_USB__ARB_EP2_INT_EN CYREG_USB_ARB_EP2_INT_EN
#define USBFS_1_USB__ARB_EP2_SR CYREG_USB_ARB_EP2_SR
#define USBFS_1_USB__ARB_EP3_CFG CYREG_USB_ARB_EP3_CFG
#define USBFS_1_USB__ARB_EP3_INT_EN CYREG_USB_ARB_EP3_INT_EN
#define USBFS_1_USB__ARB_EP3_SR CYREG_USB_ARB_EP3_SR
#define USBFS_1_USB__ARB_EP4_CFG CYREG_USB_ARB_EP4_CFG
#define USBFS_1_USB__ARB_EP4_INT_EN CYREG_USB_ARB_EP4_INT_EN
#define USBFS_1_USB__ARB_EP4_SR CYREG_USB_ARB_EP4_SR
#define USBFS_1_USB__ARB_EP5_CFG CYREG_USB_ARB_EP5_CFG
#define USBFS_1_USB__ARB_EP5_INT_EN CYREG_USB_ARB_EP5_INT_EN
#define USBFS_1_USB__ARB_EP5_SR CYREG_USB_ARB_EP5_SR
#define USBFS_1_USB__ARB_EP6_CFG CYREG_USB_ARB_EP6_CFG
#define USBFS_1_USB__ARB_EP6_INT_EN CYREG_USB_ARB_EP6_INT_EN
#define USBFS_1_USB__ARB_EP6_SR CYREG_USB_ARB_EP6_SR
#define USBFS_1_USB__ARB_EP7_CFG CYREG_USB_ARB_EP7_CFG
#define USBFS_1_USB__ARB_EP7_INT_EN CYREG_USB_ARB_EP7_INT_EN
#define USBFS_1_USB__ARB_EP7_SR CYREG_USB_ARB_EP7_SR
#define USBFS_1_USB__ARB_EP8_CFG CYREG_USB_ARB_EP8_CFG
#define USBFS_1_USB__ARB_EP8_INT_EN CYREG_USB_ARB_EP8_INT_EN
#define USBFS_1_USB__ARB_EP8_SR CYREG_USB_ARB_EP8_SR
#define USBFS_1_USB__ARB_INT_EN CYREG_USB_ARB_INT_EN
#define USBFS_1_USB__ARB_INT_SR CYREG_USB_ARB_INT_SR
#define USBFS_1_USB__ARB_RW1_DR CYREG_USB_ARB_RW1_DR
#define USBFS_1_USB__ARB_RW1_RA CYREG_USB_ARB_RW1_RA
#define USBFS_1_USB__ARB_RW1_RA_MSB CYREG_USB_ARB_RW1_RA_MSB
#define USBFS_1_USB__ARB_RW1_WA CYREG_USB_ARB_RW1_WA
#define USBFS_1_USB__ARB_RW1_WA_MSB CYREG_USB_ARB_RW1_WA_MSB
#define USBFS_1_USB__ARB_RW2_DR CYREG_USB_ARB_RW2_DR
#define USBFS_1_USB__ARB_RW2_RA CYREG_USB_ARB_RW2_RA
#define USBFS_1_USB__ARB_RW2_RA_MSB CYREG_USB_ARB_RW2_RA_MSB
#define USBFS_1_USB__ARB_RW2_WA CYREG_USB_ARB_RW2_WA
#define USBFS_1_USB__ARB_RW2_WA_MSB CYREG_USB_ARB_RW2_WA_MSB
#define USBFS_1_USB__ARB_RW3_DR CYREG_USB_ARB_RW3_DR
#define USBFS_1_USB__ARB_RW3_RA CYREG_USB_ARB_RW3_RA
#define USBFS_1_USB__ARB_RW3_RA_MSB CYREG_USB_ARB_RW3_RA_MSB
#define USBFS_1_USB__ARB_RW3_WA CYREG_USB_ARB_RW3_WA
#define USBFS_1_USB__ARB_RW3_WA_MSB CYREG_USB_ARB_RW3_WA_MSB
#define USBFS_1_USB__ARB_RW4_DR CYREG_USB_ARB_RW4_DR
#define USBFS_1_USB__ARB_RW4_RA CYREG_USB_ARB_RW4_RA
#define USBFS_1_USB__ARB_RW4_RA_MSB CYREG_USB_ARB_RW4_RA_MSB
#define USBFS_1_USB__ARB_RW4_WA CYREG_USB_ARB_RW4_WA
#define USBFS_1_USB__ARB_RW4_WA_MSB CYREG_USB_ARB_RW4_WA_MSB
#define USBFS_1_USB__ARB_RW5_DR CYREG_USB_ARB_RW5_DR
#define USBFS_1_USB__ARB_RW5_RA CYREG_USB_ARB_RW5_RA
#define USBFS_1_USB__ARB_RW5_RA_MSB CYREG_USB_ARB_RW5_RA_MSB
#define USBFS_1_USB__ARB_RW5_WA CYREG_USB_ARB_RW5_WA
#define USBFS_1_USB__ARB_RW5_WA_MSB CYREG_USB_ARB_RW5_WA_MSB
#define USBFS_1_USB__ARB_RW6_DR CYREG_USB_ARB_RW6_DR
#define USBFS_1_USB__ARB_RW6_RA CYREG_USB_ARB_RW6_RA
#define USBFS_1_USB__ARB_RW6_RA_MSB CYREG_USB_ARB_RW6_RA_MSB
#define USBFS_1_USB__ARB_RW6_WA CYREG_USB_ARB_RW6_WA
#define USBFS_1_USB__ARB_RW6_WA_MSB CYREG_USB_ARB_RW6_WA_MSB
#define USBFS_1_USB__ARB_RW7_DR CYREG_USB_ARB_RW7_DR
#define USBFS_1_USB__ARB_RW7_RA CYREG_USB_ARB_RW7_RA
#define USBFS_1_USB__ARB_RW7_RA_MSB CYREG_USB_ARB_RW7_RA_MSB
#define USBFS_1_USB__ARB_RW7_WA CYREG_USB_ARB_RW7_WA
#define USBFS_1_USB__ARB_RW7_WA_MSB CYREG_USB_ARB_RW7_WA_MSB
#define USBFS_1_USB__ARB_RW8_DR CYREG_USB_ARB_RW8_DR
#define USBFS_1_USB__ARB_RW8_RA CYREG_USB_ARB_RW8_RA
#define USBFS_1_USB__ARB_RW8_RA_MSB CYREG_USB_ARB_RW8_RA_MSB
#define USBFS_1_USB__ARB_RW8_WA CYREG_USB_ARB_RW8_WA
#define USBFS_1_USB__ARB_RW8_WA_MSB CYREG_USB_ARB_RW8_WA_MSB
#define USBFS_1_USB__BUF_SIZE CYREG_USB_BUF_SIZE
#define USBFS_1_USB__BUS_RST_CNT CYREG_USB_BUS_RST_CNT
#define USBFS_1_USB__CR0 CYREG_USB_CR0
#define USBFS_1_USB__CR1 CYREG_USB_CR1
#define USBFS_1_USB__CWA CYREG_USB_CWA
#define USBFS_1_USB__CWA_MSB CYREG_USB_CWA_MSB
#define USBFS_1_USB__DMA_THRES CYREG_USB_DMA_THRES
#define USBFS_1_USB__DMA_THRES_MSB CYREG_USB_DMA_THRES_MSB
#define USBFS_1_USB__DYN_RECONFIG CYREG_USB_DYN_RECONFIG
#define USBFS_1_USB__EP_ACTIVE CYREG_USB_EP_ACTIVE
#define USBFS_1_USB__EP_TYPE CYREG_USB_EP_TYPE
#define USBFS_1_USB__EP0_CNT CYREG_USB_EP0_CNT
#define USBFS_1_USB__EP0_CR CYREG_USB_EP0_CR
#define USBFS_1_USB__EP0_DR0 CYREG_USB_EP0_DR0
#define USBFS_1_USB__EP0_DR1 CYREG_USB_EP0_DR1
#define USBFS_1_USB__EP0_DR2 CYREG_USB_EP0_DR2
#define USBFS_1_USB__EP0_DR3 CYREG_USB_EP0_DR3
#define USBFS_1_USB__EP0_DR4 CYREG_USB_EP0_DR4
#define USBFS_1_USB__EP0_DR5 CYREG_USB_EP0_DR5
#define USBFS_1_USB__EP0_DR6 CYREG_USB_EP0_DR6
#define USBFS_1_USB__EP0_DR7 CYREG_USB_EP0_DR7
#define USBFS_1_USB__MEM_DATA CYREG_USB_MEM_DATA_MBASE
#define USBFS_1_USB__PM_ACT_CFG CYREG_PM_ACT_CFG5
#define USBFS_1_USB__PM_ACT_MSK 0x01u
#define USBFS_1_USB__PM_STBY_CFG CYREG_PM_STBY_CFG5
#define USBFS_1_USB__PM_STBY_MSK 0x01u
#define USBFS_1_USB__SIE_EP_INT_EN CYREG_USB_SIE_EP_INT_EN
#define USBFS_1_USB__SIE_EP_INT_SR CYREG_USB_SIE_EP_INT_SR
#define USBFS_1_USB__SIE_EP1_CNT0 CYREG_USB_SIE_EP1_CNT0
#define USBFS_1_USB__SIE_EP1_CNT1 CYREG_USB_SIE_EP1_CNT1
#define USBFS_1_USB__SIE_EP1_CR0 CYREG_USB_SIE_EP1_CR0
#define USBFS_1_USB__SIE_EP2_CNT0 CYREG_USB_SIE_EP2_CNT0
#define USBFS_1_USB__SIE_EP2_CNT1 CYREG_USB_SIE_EP2_CNT1
#define USBFS_1_USB__SIE_EP2_CR0 CYREG_USB_SIE_EP2_CR0
#define USBFS_1_USB__SIE_EP3_CNT0 CYREG_USB_SIE_EP3_CNT0
#define USBFS_1_USB__SIE_EP3_CNT1 CYREG_USB_SIE_EP3_CNT1
#define USBFS_1_USB__SIE_EP3_CR0 CYREG_USB_SIE_EP3_CR0
#define USBFS_1_USB__SIE_EP4_CNT0 CYREG_USB_SIE_EP4_CNT0
#define USBFS_1_USB__SIE_EP4_CNT1 CYREG_USB_SIE_EP4_CNT1
#define USBFS_1_USB__SIE_EP4_CR0 CYREG_USB_SIE_EP4_CR0
#define USBFS_1_USB__SIE_EP5_CNT0 CYREG_USB_SIE_EP5_CNT0
#define USBFS_1_USB__SIE_EP5_CNT1 CYREG_USB_SIE_EP5_CNT1
#define USBFS_1_USB__SIE_EP5_CR0 CYREG_USB_SIE_EP5_CR0
#define USBFS_1_USB__SIE_EP6_CNT0 CYREG_USB_SIE_EP6_CNT0
#define USBFS_1_USB__SIE_EP6_CNT1 CYREG_USB_SIE_EP6_CNT1
#define USBFS_1_USB__SIE_EP6_CR0 CYREG_USB_SIE_EP6_CR0
#define USBFS_1_USB__SIE_EP7_CNT0 CYREG_USB_SIE_EP7_CNT0
#define USBFS_1_USB__SIE_EP7_CNT1 CYREG_USB_SIE_EP7_CNT1
#define USBFS_1_USB__SIE_EP7_CR0 CYREG_USB_SIE_EP7_CR0
#define USBFS_1_USB__SIE_EP8_CNT0 CYREG_USB_SIE_EP8_CNT0
#define USBFS_1_USB__SIE_EP8_CNT1 CYREG_USB_SIE_EP8_CNT1
#define USBFS_1_USB__SIE_EP8_CR0 CYREG_USB_SIE_EP8_CR0
#define USBFS_1_USB__SOF0 CYREG_USB_SOF0
#define USBFS_1_USB__SOF1 CYREG_USB_SOF1
#define USBFS_1_USB__USB_CLK_EN CYREG_USB_USB_CLK_EN
#define USBFS_1_USB__USBIO_CR0 CYREG_USB_USBIO_CR0
#define USBFS_1_USB__USBIO_CR1 CYREG_USB_USBIO_CR1

/* Miscellaneous */
#define BCLK__BUS_CLK__HZ 24000000U
#define BCLK__BUS_CLK__KHZ 24000U
#define BCLK__BUS_CLK__MHZ 24U
#define CY_PROJECT_NAME "CyController_Example"
#define CY_VERSION "PSoC Creator  4.1 Update 1"
#define CYDEV_CHIP_DIE_LEOPARD 1u
#define CYDEV_CHIP_DIE_PSOC4A 16u
#define CYDEV_CHIP_DIE_PSOC5LP 2u
#define CYDEV_CHIP_DIE_PSOC5TM 3u
#define CYDEV_CHIP_DIE_TMA4 4u
#define CYDEV_CHIP_DIE_UNKNOWN 0u
#define CYDEV_CHIP_FAMILY_FM0P 5u
#define CYDEV_CHIP_FAMILY_FM3 6u
#define CYDEV_CHIP_FAMILY_FM4 7u
#define CYDEV_CHIP_FAMILY_PSOC3 1u
#define CYDEV_CHIP_FAMILY_PSOC4 2u
#define CYDEV_CHIP_FAMILY_PSOC5 3u
#define CYDEV_CHIP_FAMILY_PSOC6 4u
#define CYDEV_CHIP_FAMILY_UNKNOWN 0u
#define CYDEV_CHIP_FAMILY_USED CYDEV_CHIP_FAMILY_PSOC5
#define CYDEV_CHIP_JTAG_ID 0x2E161069u
#define CYDEV_CHIP_MEMBER_3A 1u
#define CYDEV_CHIP_MEMBER_4A 16u
#define CYDEV_CHIP_MEMBER_4D 12u
#define CYDEV_CHIP_MEMBER_4E 6u
#define CYDEV_CHIP_MEMBER_4F 17u
#define CYDEV_CHIP_MEMBER_4G 4u
#define CYDEV_CHIP_MEMBER_4H 15u
#define CYDEV_CHIP_MEMBER_4I 21u
#define CYDEV_CHIP_MEMBER_4J 13u
#define CYDEV_CHIP_MEMBER_4K 14u
#define CYDEV_CHIP_MEMBER_4L 20u
#define CYDEV_CHIP_MEMBER_4M 19u
#define CYDEV_CHIP_MEMBER_4N 9u
#define CYDEV_CHIP_MEMBER_4O 7u
#define CYDEV_CHIP_MEMBER_4P 18u
#define CYDEV_CHIP_MEMBER_4Q 11u
#define CYDEV_CHIP_MEMBER_4R 8u
#define CYDEV_CHIP_MEMBER_4S 10u
#define CYDEV_CHIP_MEMBER_4U 5u
#define CYDEV_CHIP_MEMBER_5A 3u
#define CYDEV_CHIP_MEMBER_5B 2u
#define CYDEV_CHIP_MEMBER_6A 22u
#define CYDEV_CHIP_MEMBER_FM3 26u
#define CYDEV_CHIP_MEMBER_FM4 27u
#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 23u
#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 24u
#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 25u
#define CYDEV_CHIP_MEMBER_UNKNOWN 0u
#define CYDEV_CHIP_MEMBER_USED CYDEV_CHIP_MEMBER_5B
#define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_MEMBER_USED
#define CYDEV_CHIP_DIE_ACTUAL CYDEV_CHIP_DIE_EXPECT
#define CYDEV_CHIP_REV_LEOPARD_ES1 0u
#define CYDEV_CHIP_REV_LEOPARD_ES2 1u
#define CYDEV_CHIP_REV_LEOPARD_ES3 3u
#define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3u
#define CYDEV_CHIP_REV_PSOC4A_ES0 17u
#define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17u
#define CYDEV_CHIP_REV_PSOC5LP_ES0 0u
#define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0u
#define CYDEV_CHIP_REV_PSOC5TM_ES0 0u
#define CYDEV_CHIP_REV_PSOC5TM_ES1 1u
#define CYDEV_CHIP_REV_PSOC5TM_PRODUCTION 1u
#define CYDEV_CHIP_REV_TMA4_ES 17u
#define CYDEV_CHIP_REV_TMA4_ES2 33u
#define CYDEV_CHIP_REV_TMA4_PRODUCTION 17u
#define CYDEV_CHIP_REVISION_3A_ES1 0u
#define CYDEV_CHIP_REVISION_3A_ES2 1u
#define CYDEV_CHIP_REVISION_3A_ES3 3u
#define CYDEV_CHIP_REVISION_3A_PRODUCTION 3u
#define CYDEV_CHIP_REVISION_4A_ES0 17u
#define CYDEV_CHIP_REVISION_4A_PRODUCTION 17u
#define CYDEV_CHIP_REVISION_4D_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4E_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4F_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA 0u
#define CYDEV_CHIP_REVISION_4F_PRODUCTION_256K 0u
#define CYDEV_CHIP_REVISION_4G_ES 17u
#define CYDEV_CHIP_REVISION_4G_ES2 33u
#define CYDEV_CHIP_REVISION_4G_PRODUCTION 17u
#define CYDEV_CHIP_REVISION_4H_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4I_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4J_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4K_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4L_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4M_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4N_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4O_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4P_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4Q_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4R_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4S_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4U_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_5A_ES0 0u
#define CYDEV_CHIP_REVISION_5A_ES1 1u
#define CYDEV_CHIP_REVISION_5A_PRODUCTION 1u
#define CYDEV_CHIP_REVISION_5B_ES0 0u
#define CYDEV_CHIP_REVISION_5B_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_6A_NO_UDB 0u
#define CYDEV_CHIP_REVISION_6A_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_FM3_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_FM4_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE2_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE3_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_USED CYDEV_CHIP_REVISION_5B_PRODUCTION
#define CYDEV_CHIP_REV_EXPECT CYDEV_CHIP_REVISION_USED
#define CYDEV_CONFIG_FASTBOOT_ENABLED 1
#define CYDEV_CONFIG_UNUSED_IO_AllowButWarn 0
#define CYDEV_CONFIG_UNUSED_IO CYDEV_CONFIG_UNUSED_IO_AllowButWarn
#define CYDEV_CONFIG_UNUSED_IO_AllowWithInfo 1
#define CYDEV_CONFIG_UNUSED_IO_Disallowed 2
#define CYDEV_CONFIGURATION_COMPRESSED 1
#define CYDEV_CONFIGURATION_DMA 0
#define CYDEV_CONFIGURATION_ECC 1
#define CYDEV_CONFIGURATION_IMOENABLED CYDEV_CONFIG_FASTBOOT_ENABLED
#define CYDEV_CONFIGURATION_MODE_COMPRESSED 0
#define CYDEV_CONFIGURATION_MODE CYDEV_CONFIGURATION_MODE_COMPRESSED
#define CYDEV_CONFIGURATION_MODE_DMA 2
#define CYDEV_CONFIGURATION_MODE_UNCOMPRESSED 1
#define CYDEV_DEBUG_ENABLE_MASK 0x20u
#define CYDEV_DEBUG_ENABLE_REGISTER CYREG_MLOGIC_DEBUG
#define CYDEV_DEBUGGING_DPS_Disable 3
#define CYDEV_DEBUGGING_DPS_JTAG_4 1
#define CYDEV_DEBUGGING_DPS_JTAG_5 0
#define CYDEV_DEBUGGING_DPS_SWD 2
#define CYDEV_DEBUGGING_DPS CYDEV_DEBUGGING_DPS_SWD
#define CYDEV_DEBUGGING_DPS_SWD_SWV 6
#define CYDEV_DEBUGGING_ENABLE 1
#define CYDEV_DEBUGGING_XRES 0
#define CYDEV_DMA_CHANNELS_AVAILABLE 24u
#define CYDEV_ECC_ENABLE 0
#define CYDEV_HEAP_SIZE 0x80
#define CYDEV_INSTRUCT_CACHE_ENABLED 1
#define CYDEV_INTR_RISING 0x00000001u
#define CYDEV_IS_EXPORTING_CODE 0
#define CYDEV_IS_IMPORTING_CODE 0
#define CYDEV_PROJ_TYPE 0
#define CYDEV_PROJ_TYPE_BOOTLOADER 1
#define CYDEV_PROJ_TYPE_LAUNCHER 5
#define CYDEV_PROJ_TYPE_LOADABLE 2
#define CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER 4
#define CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER 3
#define CYDEV_PROJ_TYPE_STANDARD 0
#define CYDEV_PROTECTION_ENABLE 0
#define CYDEV_STACK_SIZE 0x0800
#define CYDEV_USB_CLK_OSC_LOCKING_ENABLED_AT_PWR_UP 
#define CYDEV_USE_BUNDLED_CMSIS 1
#define CYDEV_VARIABLE_VDDA 0
#define CYDEV_VDDA 5.0
#define CYDEV_VDDA_MV 5000
#define CYDEV_VDDD 5.0
#define CYDEV_VDDD_MV 5000
#define CYDEV_VDDIO0 5.0
#define CYDEV_VDDIO0_MV 5000
#define CYDEV_VDDIO1 5.0
#define CYDEV_VDDIO1_MV 5000
#define CYDEV_VDDIO2 5.0
#define CYDEV_VDDIO2_MV 5000
#define CYDEV_VDDIO3 5.0
#define CYDEV_VDDIO3_MV 5000
#define CYDEV_VIO0 5.0
#define CYDEV_VIO0_MV 5000
#define CYDEV_VIO1 5.0
#define CYDEV_VIO1_MV 5000
#define CYDEV_VIO2 5.0
#define CYDEV_VIO2_MV 5000
#define CYDEV_VIO3 5.0
#define CYDEV_VIO3_MV 5000
#define CYIPBLOCK_ARM_CM3_VERSION 0
#define CYIPBLOCK_P3_ANAIF_VERSION 0
#define CYIPBLOCK_P3_CAN_VERSION 0
#define CYIPBLOCK_P3_CAPSENSE_VERSION 0
#define CYIPBLOCK_P3_COMP_VERSION 0
#define CYIPBLOCK_P3_DECIMATOR_VERSION 0
#define CYIPBLOCK_P3_DFB_VERSION 0
#define CYIPBLOCK_P3_DMA_VERSION 0
#define CYIPBLOCK_P3_DRQ_VERSION 0
#define CYIPBLOCK_P3_DSM_VERSION 0
#define CYIPBLOCK_P3_EMIF_VERSION 0
#define CYIPBLOCK_P3_I2C_VERSION 0
#define CYIPBLOCK_P3_LCD_VERSION 0
#define CYIPBLOCK_P3_LPF_VERSION 0
#define CYIPBLOCK_P3_OPAMP_VERSION 0
#define CYIPBLOCK_P3_PM_VERSION 0
#define CYIPBLOCK_P3_SCCT_VERSION 0
#define CYIPBLOCK_P3_TIMER_VERSION 0
#define CYIPBLOCK_P3_USB_VERSION 0
#define CYIPBLOCK_P3_VIDAC_VERSION 0
#define CYIPBLOCK_P3_VREF_VERSION 0
#define CYIPBLOCK_S8_GPIO_VERSION 0
#define CYIPBLOCK_S8_IRQ_VERSION 0
#define CYIPBLOCK_S8_SAR_VERSION 0
#define CYIPBLOCK_S8_SIO_VERSION 0
#define CYIPBLOCK_S8_UDB_VERSION 0
#define DMA_CHANNELS_USED__MASK0 0x00000003u
#define CYDEV_BOOTLOADER_ENABLE 0

#endif /* INCLUDED_CYFITTER_H */
