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Nellyw888
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VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb
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Reinforcement Learning
Transformers
Safetensors
Nellyw888/RTL-Coder_7b_reasoning_tb
Nellyw888/RTL-Coder_7b_reasoning_tb_simple
qwen2
text-generation
verilog
reasoning
rtl
text-generation-inference
arxiv:
2505.11849
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ca5bbd9
VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb
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Training in progress, step 5
ca5bbd9
verified
Nellyw888
commited on
May 15, 2025
initial commit
f2d6992
verified
Nellyw888
commited on
May 15, 2025
Nellyw888
commited on
